Xilinx - Design Reuse Methodology for ASIC and FPGA Designers.pdf

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82 System Level Reuse Issues for FPGAsThis section gives an overview of the system-level issues that are unique to FPGAs whendesigning for reuse. Generally these elements must be agreed upon or at least discussed to somelevel before starting to design the modules of the system.2.1 System Synthesis and Timing IssuesDesigners should follow the guidelines for synchronous design style, clocking and reset found inthe “Reuse Methodology Manual” by Synopsys and Mentor, “Synthesis and Simulation DesignGuide” by Xilinx or the Design Guides supplied by suppliers of EDA tools for the targetedFPGA.2.1.1 Synchronous vs. Asynchronous Design StyleRule – Avoid using latches. The system should be synchronous and register-based. Use Dregisters instead of latches. Exceptions to this rule should be made with great care and must befully documented.In the past latches have been popular for designs targeting ASICs. Although latches are a simplercircuit element then flip-flops, they add a level of complexity to the design such as ambiguoustiming. Experienced designers maybe able to take advantage of the ambiguity to improve timing.Time borrowing is used to absorb some of the delay by guaranteeing that the data is set up beforethe leading clock edge at one stage or allowing the data to arrive as late as one setup time beforethe trailing clock edge at the next stage.Example 1 D Latch Implemented with GatesVHDL:architecture BEHAV of d_latch isbeginLATCH: process (GATE, DATA)beginIf (GATE= ‘1’) thenQ
9XSI page 2-28 – X4975Figure 2 - D Latch Implemented with GatesThe problem caused by the ambiguity of latch timing, and exacerbated by time borrowing, is thatit is impossible by inspection of the circuit to determine whether the designer intended to borrowtime or the circuit is just slow. In the example of the D Latch implemented using gates, acombinatorial loop results in a hold-time requirement on DATA with respect to GATE. Sincemost synthesis tools for FPGAs do not process hold-time requirements because of the uncertaintyof routing delays, it is not recommended to implement latches with combinatorial feedbackloops. Whether the latch is implemented using the combinatorial gates or logic blocks, the timinganalysis of each latch of the design is difficult. Over a large design, timing analysis becomesimpossible. Only the original designer knows the full intent of the design. Thus, latch-baseddesign is inherently not reusable.In FPGA architectures another danger of inferring a latch from RTL code is that very few FPGAdevices have latches available in the logic blocks internal to the device. In addition, in FPGAarchitectures that do have latches available in the internal logic blocks, the function of the latchescan vary from one architecture to the next. HDL compilers infer latches from incompleteconditional expressions, such as an If statement without an Else clause. If the FPGA architecturedoes not have latch capabilities, the compiler may report an error or may implement the latchusing gates in the logic blocks function generator. If the architecture has latches available in thedevice’s input pin/pad and the latches are connected to an input port, the HDL compiler mayimplement the latch inside the input pad. Once again, only the original designer knows the fullintent of the desired implementation.2.1.3 System Clocking and Clock DistributionIn system level designing, the generation, synchronization and distribution of the clocks isessential. Special care has long been taken by ASIC designers in the layout of the clockingstructure. FPGAs have an advantage in this area since the clocking mechanisms are designed intothe device and pre-tested, balancing the clocking resources to the size and target applications ofthe device. This section takes a look at the clocking resources available to reduce and manage theimpact of clock skew and clock delay.SoC vs. SoRC – SoC clocking distribution methods such as building a balanced clock tree todistribute a single clock throughout the chip is not recommend for FPGAs designs. FPGAs havededicated clocking distribution resources and methods that efficiently utilize resources to providehigh fanout with low skew throughout the chip. These clocking resources are roughly equivalentto the high-power clock buffers found in SoC designs.
Page 1 and 2: Xilinx Design Reuse Methodologyfor
Page 3 and 4: 31 IntroductionFPGAs have changed d
Page 5 and 6: 5ASIC Design FlowFPGA Design FlowSp
Page 7: 7effectively on SoRC designs and by
Page 11 and 12: 11Neither a PLL nor a DLL can be us
Page 13 and 14: 13RAM can be used for status regist
Page 15 and 16: 15Table 1 - Example of different I/
Page 17 and 18: 17entri_enclk[63:0]in[63:0]out64 lo
Page 19 and 20: 19Guideline - We recommend careful
Page 21 and 22: 21Example 6 - VHDL example of ineff
Page 23 and 24: 232’b000 : Z = C;2’b001 : Z = D
Page 25 and 26: Guideline - Refer to the synthesis
Page 27: 274.3 Formal VerificationFormal ver

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