Xilinx - Design Reuse Methodology for ASIC and FPGA Designers.pdf

6The quality of IP for ASICs depends on whether it has been verified using a specific ASICtechnology library. The ultimate proof of the quality of the IP is that it has been implemented in adesired ASIC technology. Implementing an IP or reuse module in more than one ASICtechnology is costly. However implementing IP or reusable modules in a variety of FPGAdevices is not.Faster Testing and Manufacturing - ASICs require rigorous verification strategies to avoidmultiple cycles through manufacturing. The manufacturing and test strategies must be welldefined during the specification phase. Often different strategies must be used depending on thetype of block. Memory blocks often use BIST or some form of direct memory access to detectand troubleshoot data retention problems. Other logic such as microprocessors requires customtest structures for full or partial scan or logic BIST.FPGA designs, on the other hand, are implemented on reprogrammable devices that are 100%tested by the manufacture, before reaching the designer. In fact, FPGAs can be used to create testprograms downloadable into other non-reprogrammable devices on the board. There is no nonrecurringengineering (NRE) cost, no sign-off, and no delay while waiting for prototypes to bemanufactured. The designer controls the entire design cycle, thereby shrinking the design cycle aswell as the time to prototype. This allows essential steps such as firmware designing to occur at astage late in the design flow but actually earlier in the actual design time.Verification – ASIC technology requires strict verification before manufacturing. In largecomplex system level designs many more unexpected situations can occur. SoRC designers havea much more flexible in-system verification strategy. The designers can mix testbenchverification strategies with in-circuit testing, thereby offering faster verification without the costof accelerated simulators. Surveys of design engineers have found that the area of test vectorgeneration and vector-based verification is the least favorite part of system design process.Hardware and Software Co-Designing - Early versions of the systems prototype can be used tofacilitate software and hardware co-design.1.3 A Common Design Reuse StrategyThe dramatic improvement in FPGA architecture, pricing and design tools in the past few yearshas made it possible for ASIC and FPGA designers to share a common design methodology.Designs requiring performance in the 30 – 50 MHz range are usually implemented using a RTLsynthesis design methodology making a common ASIC and FPGA design reuse strategy possible.However, designs requiring higher performance, will usually require additional techniques uniqueto the FPGA environment. A common design and design reuse strategy provides the flexibility tochoose the best method to implement a system design without the overhead of retraining thedesign teams. In addition, one can take advantage of the design rules and guidelines found inreuse methodology manuals such as the Reuse Design Methodology Manual from Synopsys andMentor or the web-based Reuse Methodology Field Guide from Qualis.There are many challenges facing Soc/SoRC designers such as time-to-market pressures, qualityof results, increasing chip complexity, varying levels of expertise, multi-site teams andmanagement and implementation of a reuse strategy. FPGA designers are faced with theadditional challenges of architectures with varying system features, meeting difficult performancegoals and different implementation strategies. This paper addresses these unique challenges byshowing how the guidelines found in the Reuse Design Methodology Manual can be applied