Xilinx - Design Reuse Methodology for ASIC and FPGA Designers.pdf

24module critical_good (in0, in1, in2, in3, critical, out);input in0, in1, in2, in3, critical;output out;assign out = ((in0&in1) | ~in2) & ~in3 & ~critical;endmodulein0in1in2in3criticalout3.4 Tristate vs. Mux BusesFigure 15 - Critical Path after RecodingThe first consideration in designing any on-chip bus is whether to use a tristate bus or amultiplexer-based bus. Tristate buses are popular for board-level designs and are also commonlyfound in FPGA-based designs, because they reduce the number of wires and are readily availableon many FPGA devices. Tristate buses are problematic for on-chip interconnection since it isessential that only one driver is active on the bus at any one-time; any bus contention, withmultiple drivers active at the same time, can increase power consumption and reduce thereliability of the chip. There are additional problems in ASICs that do not exist for FPGAs. Forexample, ASIC designers must make sure that tristate buses are never allowed to float. FPGAtechnologies provide weak keeper circuits that pull-up the floating bus to a known value.Tristate buses are especially problematic for modules designed for reuse. There are a limitednumber of tristate resources (i.e., tristate buffers connected to interconnect) in each device familyand device size within a family. The next designer may not have enough resources available,forcing a significant redesign.Guidelines – We recommend using multiplexer-based buses when designing for reuse since theyare technology-independent and more portable.3.5 Arithmetic FunctionsFPGA architectures designed for system level integration contains dedicated carry logic circuitrythat provides fast arithmetic carry capabilities for high-speed arithmetic functions. The dedicatedcarry logic is generally inferred by the synthesis tools from an arithmetic operator (i.e., +, -, /). Inthe Xilinx Virtex architecture a 16x16 multiplier can effectively use the carry logic from themultiplier operand “*” and operate at 60MHz non-pipelined and 160MHz with pipeline stages.Many synthesis tools have libraries of pre-optimized functions, such as Synopsys DesignWarelibraries, which can be inferred from RTL code as shown in the example following.sum = a_in * b_in.