Xilinx - Design Reuse Methodology for ASIC and FPGA Designers.pdf

14systems that contain from 16 to 64kbyets of SRAM with 8-bit processor cores and 40K FPGAsystem gates.Standalone memories can provide designers with solutions when large blocks of storage areneeded for caches, buffers, and large look-up tables, such as in networking applications. Howeverthe trend in SoC designs implemented as ASICs has been towards many smaller blocks of SRAMfor local buffering, register files, and temporary storage.SoRC vs. SoC - SoRC architectures are generally designed with small to medium memorycapabilities. Standard cell devices can embed large blocks of high performance memory on-chip.High-speed SRAM (e.g. 350MHz) with features such as double-data-rate (DDR) I/O capabilitiesand zero-bus latencies and very large, multiple Gigabyte memories are best left off-chip in bothSoC and SoRC devices. Even half a megabit or more of SRAM or several megabytes of DRAM,is more cost-effective when implemented off-chip.Most SoRC FPGA devices have banks of I/Os that can be configured to interface efficiently tohigh speed SRAM and synchronous DRAM. The market is shifting away from 5-V devices tochips that are operate from 3.3V supplies and offer 3.3V LVTTL (low-voltage TTL) interfacesrather than standard TTL or CMOS I/O levels. The voltage is continuing to drop as signal swingsare reduced to improve access time and power dissipation. SRAMs are offering 2.5V I/O linesthat meet the HSTL (high-speed subterminated logic) interface specifications. These higher-speedI/O lines will allow bus operations well beyond 300MHz.SoC vs. SoRC - An advantage of designing a system using FPGA technology is that the FPGAvendor has already invested the resources to support various I/O standards. As a result, a designercan develop and prototype with a wide range of interface standards.2.3 External Operability (I/O Standards)Complex, system level chips require a variety of I/O interface standards. These different I/Ostandards provide higher levels of performance and/or lower power dissipation and are optimizedfor system-critical elements such as backplane, memory and communication systems. High-speedapplications such as 66 MHz PCI require high-speed input and output capabilities. One obvioustrend for system-level FPGA architectures is to add the necessary I/O buffers into the device toimprove the overall system performance, reduce the board size, reduce cost, simplify the designand provide full high-speed access to other devices.Rule – When designing with a reusable module, choose a SoRC device that supports the requiredI/O standards.Rule – Any module design for reuse that contains I/O should take advantage of the variety of I/Ostandards provided in the selected FPGA architecture. It is important to document the I/Ostandards required and any specific feature of the SoRC device’s I/O that was used in the initialimplementation of the sub-module.Verify that the selected architecture protects all pads from electrostatic discharge (ESD) and fromover-voltage transients. Having IEEE 1149.1-compatible boundary scan test capabilities availablein the I/O blocks can enhance board level testing.