VLSI I: von Architektur zu hochintegrierter Schaltung und FPGA

IntroductionIn this exercise, architectural transformations will be applied to a basic finite impulse response (FIR) filter in order to getseveral architecture variants that differ in cost and performance. We are then going to make simple cost analyses usingpen and paper, which will help us to derive first order estimates of the complexity and expected performance of the differentarchitectures. At the end of this exercise, a block diagram and a schedule of the preferred solution are prepared as startingpoints for register transfer level (RTL) synthesis in the next computer exercise.1. Taking advantage of architectural transforms to tailor a circuit architectureA FIR filter of order N is defined by the equationy[k] =N∑b n · x[k − n] ,n=0where k denotes consecutive, discrete timesteps. We assume that the input data x[k] and the coefficients b i are in 16 bittwo’s complement format, and that the coefficients b i are time-independent. Note that we will not worry about the detailedI/O timing in this exercise (i.e. no input or output registers have to be considered during the analysis).In the first part of the exercise, we will start with the isomorphic architecture which will then serve as a basis for variousarchitectural transforms.In order to estimate hardware cost figures such as circuit size and maximum path length, refer to appendix A where thekey parameters of some common circuit blocks are given. Note that this will result in a first order estimate which may notbe completely accurate - the main goal here is to compare the different architectures.To calculate the various figures of merit, assume that the input data is registered outside of the FIR block, and that carrylookaheadadders are being used. We neglect the area requirements for storing the coefficients. Assume that the result ofthe multiplication is truncated to 16 bit.Student Task 1:1. Isomorphic architecturea) Draw a data dependency graph (DDG) of the most straightforward implementation for a 3 rd order FIR filter(N = 3). This solution will be referred to as the isomorphic architecture throughout this exercise.b) Calculate the circuit size A, maximum path length t lp , latency L, cycles needed per data item Γ, and thethroughput Θ of this implementation a . Use the figures given in appendix A.(Hint: Do not forget to include the time needed by the registers.)c) Calculate the same characteristics for a FIR filter of order N.2. Iterative decompositiona) By means of iterative decomposition you can achieve a minimum hardware solution for a 3 rd order FIRfilter. Draw the DDG for this architecture. You may summarize the control section in one block.b) Calculate the characteristics (A, t lp , L, Γ, Θ) for this architecture and for a general FIR filter of order N.3. Pipelining Ia) We can cut down the maximum path length by introducing pipeline registers. Taking the isomorphic architectureas starting point, develop a pipelined architecture where each stage contains at most one arithmeticelement, and draw its DDG.b) Calculate the characteristics (A, t lp , L, Γ, Θ) for this architecture and for a general FIR filter of order N.4. Retiminga) Again starting from the isomorphic architecture, we can relocate functional registers by means of retimingand chain reversal. Keep in mind that this transform is easy only for constant filter coefficients. Draw aDDG for this architecture.b) Calculate the characteristics (A, t lp , L, Γ, Θ) for this architecture and for a filter order N.2