Timing and Transients in Digital Circuits - Integrated Systems ...

Institut für Integrierte SystemeIntegrated Systems LaboratoryDepartment of Information Technology and Electrical EngineeringVLSI I: von Architekturzu hochintegrierter Schaltung und FPGA227-0116-00LExercise 1Timing and Transients in Digital CircuitsProf. Dr. H. KaeslinDr. N. FelberSVN Rev.: 675Last Changed: 29-02-2012Reminder:With the execution of this training you declare that you understand and accept the regulations aboutusing CAE/CAD software installations at the ETH Zurich. These regulations can be read anytime athttp://dz.ee.ethz.ch/regulations/index.en.html.

1 What you will learnComputer science views digital circuits as ideal machines and describes their behavior using mathematicalmodels such as finite state machines and computer arithmetics. While such abstractions arevalid and useful given certain preconditions, they omit a number of effects that impact real circuits.The most important simplifications relate to transients and delays that come from the fact that noelectrical node can change its state in zero time and no physical signal can propagate in zero time.Getting the timing right is absolutely essential when designing a digital circuit, if that circuit is meant tobehave in the same way as its mathematical or computer model. Several lessons of our VLSI coursewill be devoted to data throughput, timing constraints, tradeoffs between time and energy, clockingdisciplines, sychronization, metastability, and other timing-related issues.This warm-up exercise is here to make sure you are aware of the fundamental concepts and quantitiesrequired to understand that material and to become an expert user of electronic design automation(EDA) software. More specifically, we will show you• How to capture the time-wise behavior of digital (sub)circuits.• Visual formalisms that help analyze timing issues.• The very basics of synchronous circuit operation and simulation set up.• What determines the maximum frequency at which a circuit can be clocked.• The dependencies introduced by signals entering or departing from a circuit.• Things to watch out for when designing control logic and state machines.2 Terms and Concepts2.1 Transients in digital circuitsAll circuits discussed here are digital and make use of two-valued signals. For practical reasons,the voltage levels that represent 0 and 1 respectively must be separated by some “forbidden” intervalwhere a signal has no meaningful binary interpretation and must be considered as logically undefinedor invalid. In accordance with the IEEE 1164 standard, we use the symbol X to denote situationswhere a signal is electrically driven but has no known logic value. Note that any signal that switchesfrom 0 to 1 or vice versa will transit through the forbidden interval for a brief lapse of time.Some signals may even rock back and forth a few times or exihibit short-lived voltage excursionsbefore eventually reaching their steady-state condition. As explained in appendix A.5 “Transient behaviorof logic circuits” of our textbook 1 even circuits of just a few gates must be suspected to developsuch spurious and unwanted signals, known as hazards, unless one has proof to the contrary.2.2 Combinational, sequential, and sychronous circuitsA digital circuit is qualified as combinational if its present output gets determined by its presentinput exclusively when in steady-state condition. This contrasts with sequential logic the output ofwhich depends not only on present but also on past input values. Sequential circuits must, therefore,necessarily keep their state in some kind of storage elements whereas combinational ones have no1Hubert Kaeslin, “Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication”, CambridgeUniversity Press, 2008.2

state. This is why the former are also referred to as state-holding or as memorizing, and the latteras state-less or as memoryless.Sequential networks typically consist of combinational gates and storage elements (such as flip-flops,latches, and/or some memory). Their correct operation critically depends on proper timing, that is onconsistently respecting all time-related conditions imposed by the various circuit components.As you will learn, synchronous circuits where all state transitions are triggered by one particularperiodic signal, called clock, are easier to design and safer to operate than asynchronous circuitswhere there is no (global) clock and where state transitions may occur at any time, e.g. in responseto some unanticipated hazard. We will consider synchronous circuits exclusively in this exercise.2.3 Basic timing quantitiesAs becomes clear from fig.1 and from the table below, it takes two timing quantities to capture thetime-wise behavior of combinational circuits. An additional six are required for flip-flops, latches, andmemories. 2 t su fft pd ffa)CombinationalLogicXXFFt cd ct pd ct cd ct pd cb) Flip-Flopt ho ffCLKt clk fat clk riDpositive edgetriggeredQt cd ffc)LatchCLKDt su lat ho lapassholdt clk hit clk hi t clk lot clk riCLKDQCLKt clk lot clk faDQCLK to Q D to Qpasses while highholds while lowQt cd lct pd lct cd ldt pd ldFigure 1: Timing characteristics of combinational subcircuits (a), flip-flops (b), and latches (c).2Actually, there are two more, called recovery time and home time, required to model asychronous (re)set inputs,but we will skip them at this point.3

i(k)presentinputcombinationalcircuitryt iot soo(k)presentoutputactive clock edget su t ho of stateregistersymbolsstimulus applicationt sst isresponse acquisitions(k)presentstatestate registers(k+1)nextstatet ist sst sorecording of valuesactive clock edgepassive clock edgea)CLKresponseacquisitiont iostimulusapplicationc)t sst sot ist ioo(k −1)s(k)s(k+1)i(k) o(k) i(k+1) o(k+1)i(k+2)timesignaturesdata valid "0" or "1"CLKclock signaldata invalidor unknown "X"i(.)inputhigh impedance "Z"o(.)outputdon’t care "−"b)Figure 2: Different views on circuit delays and timing. Signal propagation paths in a synchronouscircuit (a), timing diagram (b), Anceau diagram (c).5

For reasons explained in appendix 3.7 “Deriving a coherent schedule for simulation and test” of ourtextbook, we strongly recommend to have these events occur in a strictly periodic fashion and toorder them as follows △ ↓ (⊤ = □) ↑ . Each clock period thus gets subdivided into four phases. Astandard setup for a symmetric clock of 10 MHz is given below as an example.cycle events with times of occurrence [ns]k △ ↓ ⊤□ ↑0 10 50 90 1001 110 150 190 2002 210 250 290 300... ... ... ... ...2.6 Timing diagramsDiagrams help to understand the events and activities that occur during circuit operation and to capturetheir respective cause ↦→ effect and/or precedence relationships. The most popular form is the(linear) timing diagram, shown in the lower half of fig.2b below the time axis. Here the waveformsobserved at the circuit pins are reproduced a bit like on an oscilloscope. In addition, a few signatureshelp to express special data conditions such as invalid or unknown output X, a high impedancecondition Z, and a don’t care input -.The upper half of fig.2b relates the waveforms of timing diagram to the timewise separations betweenthe various periodic events in each clock cycle required to ensure proper circuit operation. Note thetwo short and fat vertical bars. The lower one indicates when the output has settled to a new valueand becomes available for data acquisition. Similarly, the upper bar tells when the computation of thenext state has come to an end and so determines the earliest point in time the circuit may be safelyclocked. Each bar can be understood as a maximum-in-time or “whichever comes later” operator.As circuit operation is periodic, there is nothing more natural than using a circular arrangement torepresent the sequence of events and their time-wise relationships. This kind of graph is known asAnceau diagram after its inventor François Anceau, see fig.2c.3 ExercisesThe simplest and most common clocking discipline is edge-triggered one-phase clocking. All registersare built from flip-flops exclusively and all flip-flops may change state either at the rising or at thefalling edge of the clock, that is once per clock period. In this exercise we presuppose this clockingscheme with a duty cycle of 50%. However, to solve some specific problems, you are free to consideralternative approaches.3.1 Timing verificationExercise 1 : Introductory exampleConsider the circuit in fig.3. t .. ff and t .. c stand for the timing quantities of the registers and combinationalcells respectively. Clock distribution is assumed to be perfect with no delay or skew t sk = 0.6

tpd ff, tcd fftsu ff, tho fftpd ff, tcd fftsu ff, tho ffDBU1QB DA QAtpd c, tcd cU2ClkxCtskFigure 3: Synchronous sequential circuit.a) What is the function of this circuit?b) State the basic timing requirements in mathematical terms!c) For a given t ho ff , which timing condition is most critical to ensure proper operation? What canyou do to alleviate this requirement?d) Assume an extremely long clock high time t hi clk . Is it possible to replace the D-type flip-flopswith D-type latches? Note from fig.1 that standard D-type latches are transparent while theclock is 1. Explain how you have arrived at your conclusion!e) For t cd c = t pd c and with t ho la being given, what is the condition that t hi clk must satisfy whenboth flip-flops are replaced by latches? Draw a timing or Anceau diagram!Exercise 2 : Timing in a linear feedback shift registerLinear feedback shift registers (LFSR) are typically used for generating sequences, e.g. for cyclicencoding or for generating pseudo-random numbers. As an example, fig.4 shows a circuit wired forCRC-4 encoding.InxSIU4D Q U5 D Q D Q D QU3U2 U1 U0ClkxCQ3xSO Q2xSO Q1xSO Q0xSOFigure 4: Cyclic coder circuitAssume the timing data below apply:Flip-flops: t pd ff = t cd ff = 0.9 ns, t su ff = 0.5 ns, t ho ff = 0.2 nsXOR gates: t pd c = t cd c = 0.8 nsa) Determine the set of signal propagation paths for this circuit according to fig.2a!b) Draw an Anceau diagram or a timing diagram for a clock period of T clk = 4.0 ns!c) Determine the maximum admissible clock speed for this circuit!7

d) Specify the valid time windows for stimulus application △ and for response acquisition ⊤ whenthe circuit is clocked at maximum rate!e) Define the interface timing parameters t pd , t su , t ho that apply when the time-wise behavior ofthis circuit is viewed from externally!Exercise 3 : Composite circuitsAs opposed to what fig.2a might suggest, digital circuits other than toy examples are not organized asone large state machine but composed from smaller subcircuits and automata that exchange signalsto coordinate overall operation. This simplifies functional verification and makes it possible to takeadvantage of specialized and efficient building blocks such as ROMs, ALUs, etc. Let us focus on thedata exchange at the interface between two such subcircuits as shown in fig.5.ABU11U1x 1U3U8U9U10ROMA5 D7U12U6U2clkU4U5CLOCK TREEU7tclk cycleclkaddressdatatclk hightsu ROM tho ROMaddress validtpd ROMprevious datatclk lowdata validFigure 5: Composite circuit (top), timing diagram of the ROM (bottom)The entire circuit runs with a clock period of T clk = 11 ns and the timing parameters of its variouscomponents are as follows.Subcircuit ARegister: t pd ff = t cd ff = 0.9 ns, t su = 0.5 ns, t ho = 0.0 ns.Buffer U2: t pd c = t cd c = 0.8 ns.Subcircuit BRegisters: t pd ff = t cd ff = 0.9 ns, t su = 0.5 ns, t ho = 0.0 ns.Combinational components (buffers, inverter, adder): t pd c = t cd c = 0.8 ns.ROM: t su ROM = 0.0 ns, t ho ROM = 2.3 ns, t pd ROM = 7 ns, see fig.5 for further details.a) Determine the external interface timing parameters t su B , t ho B , t cd A , t pd A !8

) Are there any problems related to the interface of the two subcircuits? Check the setup andhold margins!c) Verify the internal timing constraints for subcircuit B. The timing behavior of complex buildingblocks (such as ALUs) or macrocells (such as RAMs and ROMs) often differs significantly fromthat of elementary gates or flip-flops. Do you see any problems in subcircuit B?d) Find solutions to solve the problems, if any,◦ by adding combinational cells exclusively,◦ by adding different storage elements!Which solution do you prefer?3.2 Design of safe finite state machinesThis section extends our considerations to finite state machines and to circuits where a state machinecontrols other parts of the circuit such as a datapath. If you lack the necessary background tounderstand and solve the problems, you may want to consult appendix B “Finite State Machines” inour textbook to learn more about the various types of automata and how the compare.Exercise 4 : Automata types and their propertiesa) Which class of finite state machines does the circuit of fig.3 belong to? Explain why!b) What is the latency of this circuit?c) Can it possibly develop hazards at the output?d) Answer the same questions for the circuit of fig.4!Exercise 5 : Parasitic inputs and cyclesYour are tasked with devising a controller for a semi-automatic gear unit. States are low gear, secondgear, top gear, reverse gear, and neutral. There are two separate input signals, namely UpxSI andDownxSI.a) Capture the desired functionality in a state diagram!b) Complete that state diagram to make your design fault-tolerant! This means you must not onlyconsider the regular states and inputs, but the parasitic states (states which are present in abinary representation but unused) and all physically possible input combinations too.c) Pick a meaningful reset state!9

inoutcontroller1a b cU1U2U3U4controller2Figure 6: Two cross-connected state machinesExercise 6 : Interacting state machinesConsider the circuit of fig.6.a) What problems may arise when these two automata are connected together?b) Solve this problem by adding additional components to controller2!c) What type of state machine should be used for controller1 to avoid complications?10