Timing and Transients in Digital Circuits - Integrated Systems ...

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d) Specify the valid time windows for stimulus application △ and for response acquisition ⊤ whenthe circuit is clocked at maximum rate!e) Define the interface timing parameters t pd , t su , t ho that apply when the time-wise behavior ofthis circuit is viewed from externally!Exercise 3 : Composite circuitsAs opposed to what fig.2a might suggest, digital circuits other than toy examples are not organized asone large state machine but composed from smaller subcircuits and automata that exchange signalsto coordinate overall operation. This simplifies functional verification and makes it possible to takeadvantage of specialized and efficient building blocks such as ROMs, ALUs, etc. Let us focus on thedata exchange at the interface between two such subcircuits as shown in fig.5.ABU11U1x 1U3U8U9U10ROMA5 D7U12U6U2clkU4U5CLOCK TREEU7tclk cycleclkaddressdatatclk hightsu ROM tho ROMaddress validtpd ROMprevious datatclk lowdata validFigure 5: Composite circuit (top), timing diagram of the ROM (bottom)The entire circuit runs with a clock period of T clk = 11 ns and the timing parameters of its variouscomponents are as follows.Subcircuit ARegister: t pd ff = t cd ff = 0.9 ns, t su = 0.5 ns, t ho = 0.0 ns.Buffer U2: t pd c = t cd c = 0.8 ns.Subcircuit BRegisters: t pd ff = t cd ff = 0.9 ns, t su = 0.5 ns, t ho = 0.0 ns.Combinational components (buffers, inverter, adder): t pd c = t cd c = 0.8 ns.ROM: t su ROM = 0.0 ns, t ho ROM = 2.3 ns, t pd ROM = 7 ns, see fig.5 for further details.a) Determine the external interface timing parameters t su B , t ho B , t cd A , t pd A !8
) Are there any problems related to the interface of the two subcircuits? Check the setup andhold margins!c) Verify the internal timing constraints for subcircuit B. The timing behavior of complex buildingblocks (such as ALUs) or macrocells (such as RAMs and ROMs) often differs significantly fromthat of elementary gates or flip-flops. Do you see any problems in subcircuit B?d) Find solutions to solve the problems, if any,◦ by adding combinational cells exclusively,◦ by adding different storage elements!Which solution do you prefer?3.2 Design of safe finite state machinesThis section extends our considerations to finite state machines and to circuits where a state machinecontrols other parts of the circuit such as a datapath. If you lack the necessary background tounderstand and solve the problems, you may want to consult appendix B “Finite State Machines” inour textbook to learn more about the various types of automata and how the compare.Exercise 4 : Automata types and their propertiesa) Which class of finite state machines does the circuit of fig.3 belong to? Explain why!b) What is the latency of this circuit?c) Can it possibly develop hazards at the output?d) Answer the same questions for the circuit of fig.4!Exercise 5 : Parasitic inputs and cyclesYour are tasked with devising a controller for a semi-automatic gear unit. States are low gear, secondgear, top gear, reverse gear, and neutral. There are two separate input signals, namely UpxSI andDownxSI.a) Capture the desired functionality in a state diagram!b) Complete that state diagram to make your design fault-tolerant! This means you must not onlyconsider the regular states and inputs, but the parasitic states (states which are present in abinary representation but unused) and all physically possible input combinations too.c) Pick a meaningful reset state!9
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