Timing and Transients in Digital Circuits - Integrated Systems ...

i(k)presentinputcombinationalcircuitryt iot soo(k)presentoutputactive clock edget su t ho of stateregistersymbolsstimulus applicationt sst isresponse acquisitions(k)presentstatestate registers(k+1)nextstatet ist sst sorecording of valuesactive clock edgepassive clock edgea)CLKresponseacquisitiont iostimulusapplicationc)t sst sot ist ioo(k −1)s(k)s(k+1)i(k) o(k) i(k+1) o(k+1)i(k+2)timesignaturesdata valid "0" or "1"CLKclock signaldata invalidor unknown "X"i(.)inputhigh impedance "Z"o(.)outputdon’t care "−"b)Figure 2: Different views on circuit delays and timing. Signal propagation paths in a synchronouscircuit (a), timing diagram (b), Anceau diagram (c).5