Sample Solution Written Exam in VLSI I - Integrated Systems ...

(b) On which part of the VLSI design flow where the practical exercises of the VLSI 1 ( 1 / 2 )lecture based on? Select the correct answer.A. Front-end design B. Back-end design(c) Select for each statement whether it is true or false.i) Logic simulation, timing verification and electrical rule check (ERC) are used ( 1 / 2 )to validate gate-level schematics or net lists.A. True B. Falseii) Design for test (DFT) allows the improvement of the controllability and observabilityof the inner circuit nodes without adding auxiliary( 1 / 2 )circuitry.A. True B. Falseiii) In the floor planning step, each cell is assigned to a specific location. After ( 1 / 2 )that the metal wires, carrying the electrical signals between the cells, aredefined.A. True B. Falseiv) Layout versus schematic (LVS) verifies the conformity of the layout with geometricrules given by the technology( 1 / 2 )used.A. True B. FalseProblem 3: Field-programmable logic(a) Encircle the correct characteristic in each cell of the table.(3)Configuration Non- Reconfi- Unlimited Radiationtechnology volatile gurable endurance toleranceSRAM yes / no in / out yes / no good / poorof circuitEPROM yes / no in / out yes / no good / poorof circuitEEPROM yes / no in / out yes / no good / poorof circuit(b) The organization of hardware resources of field-programmable logic can be dividedinto two classes: complex programmable logic devices (CPLD) and fieldprogrammablegate arrays (FPGA).Select for each statement whether it is true for CPLDs, for FPGAs or for both.i) This class(es) consist of many simple programmable logic devices.( 1 / 2 )A. CPLD B. FPGAPage 2 of 30VLSI I Exam Summer 2009

ii) The logic AND-operation between two 10-bit input vectors can be realized in ( 1 / 2 )general with:A. CPLD B. FPGAiii) Which class of devices is better suited to realize a prototype for the upcoming ( 1 / 2 )WirelessHD standard?A. CPLD B. FPGAiv) Look-up tables and switch boxes can be found in( 1 / 2 )A. CPLD B. FPGAv) What is the difference between a fine-grained FPGA architecture and a coarsegrainedFPGA(1)architecture?vi) The following figures, Fig. 1, Fig. 2, and Fig. 3, each shows a logic cell of (1 1 / 2 )an FPGA family. Please note for each logic cell whether it is a fine-grainedarchitecture or a coarse-grained architecture.The adaptive logic module cell shown in Fig. 1 belongs to aA. fine-grained architecture B. coarse-grained architectureThe VersaTile cell in Fig. 2 of an Actel FPGA belongs to aA. fine-grained architecture B. coarse-grained architectureThe Virtex-4 slice in Fig. 3 of a Xilinx FPGA belongs to aA. fine-grained architecture B. coarse-grained architecturePage 3 of 30VLSI I Exam Summer 2009

Figure 1: An adaptive logic module of a Altera FPGAFigure 2: A logic VersaTile cell of an Actel FPGA.Page 4 of 30VLSI I Exam Summer 2009

Figure 3: A Virtex-4 slice of a Xilinx FPGAPage 5 of 30VLSI I Exam Summer 2009

2 From Algorithms to Architectures . . . . . . . . . . . . . . . . (50 points)Problem 1: Decide whether the following statements are correct. Give a short explanation for yourdecision.(a) The user interface of a mobile phone is better implemented using dedicated hardwareinstead of general purpose hardware to meet the stringent low-power require-(1 1 / 2 )ments.(b) The video decoder of a DVD player is preferably implemented using ASIPs rather (1 1 / 2 )than dedicated hardware if the flexibility to quickly support new encoding standardsis more important than area and power efficiency.(c) A data dependency graph does not allow any circular paths of weight zero. (1 1 / 2 )(d) The AT-product can not be significantly reduced when the architecture is transformedusing iterative(1 1 / 2 )decomposition.(e) Coarse-grained pipelining can reduce the power consumption of a circuit.(1 1 / 2 )(f) Even for very small memories the area can be significantly reduced when the (1 1 / 2 )implementation is changed from registers to on-chip DRAM.Page 6 of 30VLSI I Exam Summer 2009

(a) Iterative architecturei) Draw a block diagram of the iterative algorithm. In each clock cycle, one (4)CORDIC iteration should be computed. The control path (including the calculationof d i ) can be neglected. Use only blocks given in Fig. 5. x(0), y(0), z(0)are the inputs of your circuit and x(N), y(N), z(N) the outputs after N iterations.ii) Calculate area, maximum frequency, and latency of this architecture for N=3 (2)iterations (all timing parameters not given in Fig. 5 are negligible).iii) Assume one pipeline stage is introduced in all loops. Can this help to improve (2)the throughput? Explain!Page 8 of 30VLSI I Exam Summer 2009

(b) Fully parallel architecturei) The iterations can also be unrolled such that feedback loops are no longer (4)present. Draw the unrolled architecture for N=3 iterations. As before, useblocks from Fig. 5 and neglect all control signals.ii) One of the combinational blocks in the unrolled architecture can be significantlysimplified in hardware compared to the iterative implementation. Iden-(3)tify this block and give new area and propagation delay estimations for thisblock.iii) Calculate area, maximum frequency, and latency of the unrolled architecture (2)for N=3 iterations. (If the previous task was not solved, use the originalvalues for area and propagation delay of all blocks).iv) How can the throughput of the new architecture be raised 3 times without (2)large area overhead? Name the architecture transformation and describe thechanges.Page 9 of 30VLSI I Exam Summer 2009

(c) If area efficiency is the most important goal and latency is no issue, an iterative bitserialarchitecture is the best solution. Draw a block diagram of such a CORDIC(5)architecture. Assume 8 bit word-width for all data signals and N=3 iterations.Data are fed LSB first. Use the iterative architecture as a starting point and,instead of the add/sub block, use the serial add/sub block in Fig. 6 that alreadyincludes a register for the carry-bit and its correct handling. Again, the controlsignals can be neglected.add/subrstFigure 6: Bit-serial adder(d) Bonus question: Rotation is not the only function of the CORDIC. Find a rule (2)for the calculation of d i such that z approaches the angle between the vector (x, y)and the x-axis (i.e. z → tan −1 (y/x)).Page 10 of 30VLSI I Exam Summer 2009

Problem 3: Consider the data dependency graph in Fig. 7. The input x[n] is real valued. Usef(x) = x 2 .x[n]c c c c0 1 2 3f(x)f(x) f(x) f(x)max max maxy[n]Figure 7: DDG(a) Find a mathematical expression describing the DDG above.(1)(b) A possible hardware implementation is the isomorphic architecture. Describe how (2)this architecture is obtained from a DDG.(c) How can the ’max’ operations be reordered to shorten the critical path? Which (2)algebraic property of this function is used?(d) Commutativity and distributivity of multiplications allow to reduce the total numberof multiplications in this circuit. Draw the modified(3)DDG.Page 11 of 30VLSI I Exam Summer 2009

(e) Re-timing can shorten the critical path of the circuit in Fig. 7. Perform a retimingof all three registers and draw the resulting DDG. Which operation must(2)be performed before re-timing is possible?(f) Does re-timing have an effect on latency?(1)(g) What is a systolic DDG? Which transforms must be performed on the DDG in (4)Fig. 7 to obtain a systolic DDG? Draw the resulting DDG.Page 12 of 30VLSI I Exam Summer 2009

3 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (19 points)Problem 1: Testbenches and test cases.(a) Why is it dangerous for VLSI designers to define critical test cases for functional (1)verification of their own designs?(b) Why is a hard-coded testbench often ill-suited for functional verification? When (1)can a hard-coded testbench nonetheless be useful?(c) What is the advantage of file-based over golden-model-based testbenches?(1)(d) Consider the testbench setup in Fig. 8.stimuliappliappligoldenmodeldesignunder testexpout(1)expout(2)out(1)out(2)acquifor k = 1:2result = true;if out(k) ~= expout(k)result = false;endendreportFigure 8: Testbench setup.i) What type of testbench is it?(1 1 / 2 )ii) The response and actual response comparison is (pseudo-)coded in the figure. (1)What is the problem with this comparison function (acqui)?iii) Briefly describe a strategy to detect such flaws in the testbench.(1)Page 13 of 30VLSI I Exam Summer 2009

Problem 2: Verification example.Have a look at the VHDL code in Listing 1.(a) Draw an RTL block diagram, using flip-flops with active low reset, positive edgetriggeredclock input, and an enable(1 1 / 2 )signal.(b) Provide a lower bound for the number of clock cycles for exhaustive verification (2)(formula and numerical value). Does this bound hold with equality (in general)?Explain your reasoning.(c) i) Considering the inputs of the circuit, how can you reduce the verification (1)effort while still verifying most of the functionality?ii) For non-exhaustive verification in general, how can you make sure to detect (1)functional bugs?Page 14 of 30VLSI I Exam Summer 2009

(d) Draw a timing diagram with multiple clock cycles and indicate the simulation (2)events with respect to the clock signal. With an arrow, indicate the correspondenceof one data stimuli (InputxDI) application event with its response acquisition.(e) For the rest of this exercise, assume that the reset and enable signals are logicallyhigh (’1’), and can therefore be omitted.i) Draw a state transition diagram.(2)ii) Find a minimum-length input sequence to ensure exhaustive verification. (2)iii) In one sentence, formulate a general condition for exhaustive verification using (1)state-diagram terms (edges and vertices).Page 15 of 30VLSI I Exam Summer 2009

4 Modelling Hardware with VHDL . . . . . . . . . . . . . . . . . . (37 points)Problem 1: Hardware synthesis(a) Several computer languages exist for modelling digital hardware on register transferlevel. Which languages do you know? Please name at least(1)two.(b) Which of the following statements are correct? Mark the correct statements with (2)a cross.A. VHDL does not need a special concept for handling time as it describeshardware that is synthesized into gates.B. VHDL provides statements to describe circuit hierarchy.C. VHDL can only be used to describe digital circuits.D. Concurrency can be expressed in VHDL.E. VHDL instances are always tied to some fixed input word width.F. Timing-related VHDL constructs do not impose target requirements forthe synthesis process.Problem 2: (a) Mark the correct statements below regarding bidirectional buses with a cross. (1 1 / 2 )A. The data-type for bidirectional buses must be std_ulogic orstd_ulogic_vector.B. It is not possible to drive a signal from multiple processes unless a resolutionfunction is defined.C. To model a bidirectional bus in VHDL, each driving input to the buscan be described by a conditional signal assignments and is set to ’0’when not enabled.D. It is not possible to use variables to describe a bidirectional bus.(b) When does a process statement exhibit sequential behavior? Mark the correct (1 1 / 2 )statements below with a cross.A. When the process fails to assign a value to its output signals for everypossible combination of values of its inputs.B. When a signal representing a clock (e.g., ClkxCI ) is present in a processstatement.C. When the label of the process statement contains the keyword memzing.D. When a process statement includes variables that get assigned no valuebefore being used.E. When a process includes multiple wait on statements.Page 16 of 30VLSI I Exam Summer 2009

(c) Initialization and reset mechanism.i) Mark the correct statements.(1)A. Initialization of a signal in the signal declaration part and a signalassignment in the reset clause of a sequential process lead to thesame implementation result.B. Signal initialization is for simulation purposes only.C. A hardware reset mechanism brings a circuit into a predeterminedstate at any time.ii) A register RegxDP with the following properties is to be designed. The clock (3)signal is called ClkxCI.• An asynchronous active-low reset mechanism. The reset value of the registeris all zero. The name of the reset signal is RstxRBI.• A synchronous load that sets the Register RegxDP to all ones when LoadxSIis asserted.• A synchronous enable EnaxEI that makes the signal RegxDN to the newregister content when enabled.• The load signal LoadxSI has priority over the enable signal EnaxEI.Assume that all signals are correctly declared. Write the VHDL process statementsfor this register specification.Page 17 of 30VLSI I Exam Summer 2009

Problem 3: Binary-to-BCD conversionIn Listing 2, the top-level entity of a binary-to-BCD converter is shown. In binarycoded decimal (BCD) format, a decimal number is represented as a sequence of 4-bitBCD digits. A binary-to-BCD conversion circuit converts a binary number to the BCDformat. For example, the binary number ”0010 0000 0000” becomes ”0101 0001 0010”(i.e., 512 10 ) after conversion.(a) Draw the high-level block diagram of the binary-to-BCD conversion circuit for (4)N = 3. Only Listing 2 needs to be considered. For the moment, the instantiatedcomponent Digit can be regarded as black box. Your block diagram shall visualize:• the names and hierarchy of the entities• the connectivity of the blocks and the word width of the signals• the contribution of each block to the signal BcdOutxDO.• the breakdown of the signal ModVecxD(b) Listing 3 describes the entity “Digit”.i) How many concurrent processes can you find in Listing 3?(1)Page 18 of 30VLSI I Exam Summer 2009

ii) Reformulate the process statement from line 38 to line 46 as selected signal (2)assignment.iii) Please describe at least three major differences between the process statement (2)and a concurrent/selected/conditional signal assignment.(c) Now, we consider both Listing 2 and Listing 3 and we choose N = 3.i) How many flip-flops do you expect when synthesizing this BCD-conversion (1)circuit?ii) How many clock cycles does it take to convert a 12-bit BCD number (N = 3) (2)and what is the latency of this circuit?iii) Bonus question: do not spend to much time on this question.(2)In a first version of the BCD-converter, the process statement in Listing 3,line 24–51 was replaced by the process statement given in Listing 4. Can youexplain why the simulation with the process from Listing 4 was not working asexpected, while with the current version of the entity “Digit”, the simulationresult was correct?iv) Rewrite the process statement of Listing 4 (line 1 to line 11) without using (2)the process statement construct. You are allowed to use as many new signalsPage 19 of 30VLSI I Exam Summer 2009

as you might need. Please declare them properly.Problem 4: State machines and testbenches.(a) A finite state machine (FSM) can be described in a single process statement ordistributed over two or more concurrent processes.i) Which way is preferred and leads to better results? Why?(2)ii) Draw a diagram/schematic/skeleton of the preferred coding scheme for a synchronousMealy machine. It shall visualize:(3)• the number of processes used• registers and combinational operations• input, output, and clockPage 20 of 30VLSI I Exam Summer 2009

(b) What is a testbench good for? Mark the correct answer(s).(1)A. It applies stimuli to the design under test.B. It reports the maximum clock frequency of the design under test.C. A testbench must be synthesizable in order to verify the timing of thefinal circuit.D. Assertion statements can be used in a testbench to report potentialdesign flaws.Problem 5: Event-driven simulation.(a) What are the three steps involved in an event-driven simulation? Explain them (3)with a few words.(b) Explain the difference between a signal and a variable with respect to the event (2)queue.Page 21 of 30VLSI I Exam Summer 2009

5 The Case for Synchronous Design . . . . . . . . . . . . . . . . . (21 points)Problem 1: Warm up.(a) Describe two disadvantages of synchronous circuit operation.(2)(b) What are the two guiding principles of synchronous design?(2)Problem 2: Clocking disciplines and hazards.Mark all the correct answers.(a) Which clocking disciplines allow for an arbitrary slow clock frequency?(1)A. Synchronous edge-triggered clockingB. Self-timedC. Ad hoc asynchronous(b) Where are hazards allowed?(1)A. On the write line of an asynchronous RAMB. On the synchronous preset port of flip-flop registersC. On the state signal of a FSM in a synchronous designD. On all signals in a self-timed design(c) Which statements regarding self-timed clocking are correct?(1)A. Hazard-suppression logic is not necessary.B. A global signal is necessary to control the handshake signal.C. Self-timed clocking helps to avoid problems at the circuit interfaces.D. It is possible to achieve a better performance than worst-case with selftimedclocking.Page 22 of 30VLSI I Exam Summer 2009

Problem 3: Synchronous designClkxCBlock BBlock Ameans level sensitivemeans single edge triggeredFigure 9: Circuit extracted out of a larger design.(a) Mark the clocking discipline of the circuit extract in Fig. 9(1)A. Synchronous edge-triggered clockingB. Asynchronous clockingC. Clock-as-clock-canD. Self-timed clocking(b) Explain the functionality of block A in Fig. 9 and explain potential problems with (3)this design.(c) Bonus question: Give an alternative solution that avoids this problem by only (2)altering block A only.Page 23 of 30VLSI I Exam Summer 2009

(d) Describe an alternative solution with the same functionality that also avoids the (2)aforementioned problem and is obtained by a modification in block B.Page 24 of 30VLSI I Exam Summer 2009

Problem 4: Fig. 10 shows a sequential circuit. All non zero timing parameters are marked in Fig. 10(e.g., neglect the propagation delay of the multiplexer).ClkxCRstxRBt sk,clkt sk,rstt pdt su , t hot pd c1 , t cd c1t pdt su , t hot pd c2 , t cd c2Figure 10: Sequential circuit with timing parameters.(a) Explain the additional functionality required to assure correct execution of this (3)circuit under all circumstances? Consider the circuit in Fig. 10 as a top-levelentity that is directly connected to an external quartz oscillator and reset button.Draw a block diagram of the additional functionality.Page 25 of 30VLSI I Exam Summer 2009

(b) Given the added functionality. What is the maximum value for t sk,rst ? (Assume (1)that the setup time for the reset pin of the employed flip-flop registers is zero.)(c) What is the minimum clock period for this circuit?(2)Page 26 of 30VLSI I Exam Summer 2009

Listings1 library i e e e ;2 use i e e e . std_logic_1164 . a l l ;3 use i e e e . numeric_std . a l l ;45 entity f b c i r c u i t i s67 port (8 InputxDI : in s t d _ l o g i c ;9 OutputxDO : out s t d _ l o g i c ;10 ClkxCI : in s t d _ l o g i c ;11 RstxRBI : in s t d _ l o g i c ;12 EnablexSI : in s t d _ l o g i c ) ;1314 end f b c i r c u i t ;1516 architecture r t l of f b c i r c u i t i s1718 signal Reg1xDP , Reg1xDN : s t d _ l o g i c ;19 signal Reg2xDP , Reg2xDN : s t d _ l o g i c ;2021 begin −− r t l2223 p_seq : process ( ClkxCI , RstxRBI )24 begin −− p r o c e s s p_seq25 i f RstxRBI = ’ 0 ’ then −− asynchronous r e s e t ( a c t i v e low )26 Reg1xDP

1 library IEEE ;2 use IEEE . std_logic_1164 . a l l ;34 entity BCDConv i s5 generic (N : p o s i t i v e ) ; −− number o f d i g i t s6 port ( ClkxCI : in s t d _ l o g i c ;7 RstxRBI : in s t d _ l o g i c ;8 I n i t x S I : in s t d _ l o g i c ; −− i n i t i a l i s e conversion9 ModInxDI : in s t d _ l o g i c ; −− carry in from o u t s i d e10 ModOutxDO : out s t d _ l o g i c ; −− carry out11 BcdOutxDO : out s t d_logic_vector (4∗N −1 downto 0) −− BCD r e s u l t12 ) ;13 end ;1415 architecture RTL of BCDConv i s1617 component D i g i t18 port (19 ClkxCI : in s t d _ l o g i c ;20 RstxRBI : in s t d _ l o g i c ;21 I n i t x S I : in s t d _ l o g i c ;22 ModInxDI : in s t d _ l o g i c ;23 ModOutxDO : out s t d _ l o g i c ;24 BcdOutxDO : out s t d_logic_vector (3 downto 0 ) ) ;25 end component ;2627 signal ModVecxD : s t d _ logic_vector (1 to N+1);2829 begin3031 g1 : for I in 1 to N generate32 c1 : D i g i t33 port map (34 ClkxCI => ClkxCI ,35 RstxRBI => RstxRBI ,36 I n i t x S I => I n i t x S I ,37 ModInxDI => ModVecxD( I +1) ,38 ModOutxDO => ModVecxD( I ) ,39 BcdOutxDO => BcdOutxDO( I ∗4−1 downto I ∗4 −4));40 end generate ;4142 ModOutxDO

1 library IEEE ;2 use IEEE . std_logic_1164 . a l l ;34 entity D i g i t i s5 port ( ClkxCI : in s t d _ l o g i c ;6 RstxRBI : in s t d _ l o g i c ; −− asynchronous r e s e t ( a c t i v e low )7 I n i t x S I : in s t d _ l o g i c ; −− i n i t i a l i s e t h e BCD c onversion8 ModInxDI : in s t d _ l o g i c ; −− modulus in from l e s s s i g n i f i c a n t d i g i t9 ModOutxDO : out s t d _ l o g i c ; −− modulus out to more s i g n i f i c a n t d i g i t10 BcdOutxDO : out s t d_logic_vector (3 downto 0) −− BCD output11 ) ;12 end ;1314 architecture RTL of D i g i t i s15 signal BcdInternxDP , BcdInternxDN : std_logic_vector (3 downto 0 ) ;16 signal NextModOutxS : s t d _ l o g i c ;17 begin1819 −− C a l c u l a t e t h e s h i f t in t h e BCD r e g i s t e r . Numbers between20 −− 0 and 4 i n c l u s i v e are doubled , by s h i f t i n g by 1 .21 −− Numbers from 5 to 9 i n c l u s i v e g e t mapped to 10 , 12 , 14 ,22 −− 16 , 18. This g i v e s an modout o f 1 ( i . e . a carry to t h e23 −− next d i g i t ) , and t h e v a l u e s 0 , 2 , 4 , 6 , 8 .24 BCDdoubler : process ( BcdInternxDP , ModInxDI )25 begin26 case BcdInternxDP i s27 when " 0000 " =>28 BcdInternxDN (3 downto 1) 30 BcdInternxDN (3 downto 1) 32 BcdInternxDN (3 downto 1) 34 BcdInternxDN (3 downto 1) 36 BcdInternxDN (3 downto 1) 38 BcdInternxDN (3 downto 1) 40 BcdInternxDN (3 downto 1) 42 BcdInternxDN (3 downto 1) 44 BcdInternxDN (3 downto 1) 46 BcdInternxDN (3 downto 1) 48 BcdInternxDN (3 downto 1) ’ − ’);49 end case ;50 BcdInternxDN ( 0 )

52 −− i f t h e numbers are g r e a t e r than 5 , we s h o u l d g e n e r a t e a53 −− carry out ( modulus out ) to t h e next d i g i t .54 ModOutGen : process ( BcdInternxDP )55 begin56 case BcdInternxDP i s57 when " 0101 " | " 0110 " | " 0111 " | " 1000 " | " 1001 " =>58 NextModOutxS 60 NextModOutxS