Sample Solution Written Exam in VLSI I - Integrated Systems ...

Listings1 library i e e e ;2 use i e e e . std_logic_1164 . a l l ;3 use i e e e . numeric_std . a l l ;45 entity f b c i r c u i t i s67 port (8 InputxDI : in s t d _ l o g i c ;9 OutputxDO : out s t d _ l o g i c ;10 ClkxCI : in s t d _ l o g i c ;11 RstxRBI : in s t d _ l o g i c ;12 EnablexSI : in s t d _ l o g i c ) ;1314 end f b c i r c u i t ;1516 architecture r t l of f b c i r c u i t i s1718 signal Reg1xDP , Reg1xDN : s t d _ l o g i c ;19 signal Reg2xDP , Reg2xDN : s t d _ l o g i c ;2021 begin −− r t l2223 p_seq : process ( ClkxCI , RstxRBI )24 begin −− p r o c e s s p_seq25 i f RstxRBI = ’ 0 ’ then −− asynchronous r e s e t ( a c t i v e low )26 Reg1xDP