Sample Solution Written Exam in VLSI I - Integrated Systems ...

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as you might need. Please declare them properly.Problem 4: State machines and testbenches.(a) A finite state machine (FSM) can be described in a single process statement ordistributed over two or more concurrent processes.i) Which way is preferred and leads to better results? Why?(2)ii) Draw a diagram/schematic/skeleton of the preferred coding scheme for a synchronousMealy machine. It shall visualize:(3)• the number of processes used• registers and combinational operations• input, output, and clockPage 20 of 30VLSI I Exam Summer 2009
(b) What is a testbench good for? Mark the correct answer(s).(1)A. It applies stimuli to the design under test.B. It reports the maximum clock frequency of the design under test.C. A testbench must be synthesizable in order to verify the timing of thefinal circuit.D. Assertion statements can be used in a testbench to report potentialdesign flaws.Problem 5: Event-driven simulation.(a) What are the three steps involved in an event-driven simulation? Explain them (3)with a few words.(b) Explain the difference between a signal and a variable with respect to the event (2)queue.Page 21 of 30VLSI I Exam Summer 2009
Page 4 and 5: (b) On which part of the VLSI desig
Page 6 and 7: Figure 1: An adaptive logic module
Page 8: 2 From Algorithms to Architectures
Page 11 and 12: (b) Fully parallel architecturei) T
Page 13 and 14: Problem 3: Consider the data depend
Page 15 and 16: 3 Functional Verification . . . . .
Page 17 and 18: (d) Draw a timing diagram with mult
Page 19 and 20: (c) Initialization and reset mechan
Page 21: ii) Reformulate the process stateme
Page 25 and 26: Problem 3: Synchronous designClkxCB
Page 27 and 28: Problem 4: Fig. 10 shows a sequenti
Page 29 and 30: Listings1 library i e e e ;2 use i
Page 31 and 32: 1 library IEEE ;2 use IEEE . std_lo

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