Sample Solution Written Exam in VLSI I - Integrated Systems ...

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4 Modelling Hardware with VHDL . . . . . . . . . . . . . . . . . . (37 points)Problem 1: Hardware synthesis(a) Several computer languages exist for modelling digital hardware on register transferlevel. Which languages do you know? Please name at least(1)two.(b) Which of the following statements are correct? Mark the correct statements with (2)a cross.A. VHDL does not need a special concept for handling time as it describeshardware that is synthesized into gates.B. VHDL provides statements to describe circuit hierarchy.C. VHDL can only be used to describe digital circuits.D. Concurrency can be expressed in VHDL.E. VHDL instances are always tied to some fixed input word width.F. Timing-related VHDL constructs do not impose target requirements forthe synthesis process.Problem 2: (a) Mark the correct statements below regarding bidirectional buses with a cross. (1 1 / 2 )A. The data-type for bidirectional buses must be std_ulogic orstd_ulogic_vector.B. It is not possible to drive a signal from multiple processes unless a resolutionfunction is defined.C. To model a bidirectional bus in VHDL, each driving input to the buscan be described by a conditional signal assignments and is set to ’0’when not enabled.D. It is not possible to use variables to describe a bidirectional bus.(b) When does a process statement exhibit sequential behavior? Mark the correct (1 1 / 2 )statements below with a cross.A. When the process fails to assign a value to its output signals for everypossible combination of values of its inputs.B. When a signal representing a clock (e.g., ClkxCI ) is present in a processstatement.C. When the label of the process statement contains the keyword memzing.D. When a process statement includes variables that get assigned no valuebefore being used.E. When a process includes multiple wait on statements.Page 16 of 30VLSI I Exam Summer 2009
(c) Initialization and reset mechanism.i) Mark the correct statements.(1)A. Initialization of a signal in the signal declaration part and a signalassignment in the reset clause of a sequential process lead to thesame implementation result.B. Signal initialization is for simulation purposes only.C. A hardware reset mechanism brings a circuit into a predeterminedstate at any time.ii) A register RegxDP with the following properties is to be designed. The clock (3)signal is called ClkxCI.• An asynchronous active-low reset mechanism. The reset value of the registeris all zero. The name of the reset signal is RstxRBI.• A synchronous load that sets the Register RegxDP to all ones when LoadxSIis asserted.• A synchronous enable EnaxEI that makes the signal RegxDN to the newregister content when enabled.• The load signal LoadxSI has priority over the enable signal EnaxEI.Assume that all signals are correctly declared. Write the VHDL process statementsfor this register specification.Page 17 of 30VLSI I Exam Summer 2009
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