Sample Solution Written Exam in VLSI I - Integrated Systems ...

More documents

Recommendations

Info

Problem 3: Binary-to-BCD conversionIn Listing 2, the top-level entity of a binary-to-BCD converter is shown. In binarycoded decimal (BCD) format, a decimal number is represented as a sequence of 4-bitBCD digits. A binary-to-BCD conversion circuit converts a binary number to the BCDformat. For example, the binary number ”0010 0000 0000” becomes ”0101 0001 0010”(i.e., 512 10 ) after conversion.(a) Draw the high-level block diagram of the binary-to-BCD conversion circuit for (4)N = 3. Only Listing 2 needs to be considered. For the moment, the instantiatedcomponent Digit can be regarded as black box. Your block diagram shall visualize:• the names and hierarchy of the entities• the connectivity of the blocks and the word width of the signals• the contribution of each block to the signal BcdOutxDO.• the breakdown of the signal ModVecxD(b) Listing 3 describes the entity “Digit”.i) How many concurrent processes can you find in Listing 3?(1)Page 18 of 30VLSI I Exam Summer 2009
ii) Reformulate the process statement from line 38 to line 46 as selected signal (2)assignment.iii) Please describe at least three major differences between the process statement (2)and a concurrent/selected/conditional signal assignment.(c) Now, we consider both Listing 2 and Listing 3 and we choose N = 3.i) How many flip-flops do you expect when synthesizing this BCD-conversion (1)circuit?ii) How many clock cycles does it take to convert a 12-bit BCD number (N = 3) (2)and what is the latency of this circuit?iii) Bonus question: do not spend to much time on this question.(2)In a first version of the BCD-converter, the process statement in Listing 3,line 24–51 was replaced by the process statement given in Listing 4. Can youexplain why the simulation with the process from Listing 4 was not working asexpected, while with the current version of the entity “Digit”, the simulationresult was correct?iv) Rewrite the process statement of Listing 4 (line 1 to line 11) without using (2)the process statement construct. You are allowed to use as many new signalsPage 19 of 30VLSI I Exam Summer 2009
Page 4 and 5: (b) On which part of the VLSI desig
Page 6 and 7: Figure 1: An adaptive logic module
Page 8: 2 From Algorithms to Architectures
Page 11 and 12: (b) Fully parallel architecturei) T
Page 13 and 14: Problem 3: Consider the data depend
Page 15 and 16: 3 Functional Verification . . . . .
Page 17 and 18: (d) Draw a timing diagram with mult
Page 19: (c) Initialization and reset mechan
Page 23 and 24: (b) What is a testbench good for? M
Page 25 and 26: Problem 3: Synchronous designClkxCB
Page 27 and 28: Problem 4: Fig. 10 shows a sequenti
Page 29 and 30: Listings1 library i e e e ;2 use i
Page 31 and 32: 1 library IEEE ;2 use IEEE . std_lo

Sample Solution Written Exam in VLSI I - Integrated Systems ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?