Sample Solution Written Exam in VLSI I - Integrated Systems ...

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(e) Re-timing can shorten the critical path of the circuit in Fig. 7. Perform a retimingof all three registers and draw the resulting DDG. Which operation must(2)be performed before re-timing is possible?(f) Does re-timing have an effect on latency?(1)(g) What is a systolic DDG? Which transforms must be performed on the DDG in (4)Fig. 7 to obtain a systolic DDG? Draw the resulting DDG.Page 12 of 30VLSI I Exam Summer 2009
3 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (19 points)Problem 1: Testbenches and test cases.(a) Why is it dangerous for VLSI designers to define critical test cases for functional (1)verification of their own designs?(b) Why is a hard-coded testbench often ill-suited for functional verification? When (1)can a hard-coded testbench nonetheless be useful?(c) What is the advantage of file-based over golden-model-based testbenches?(1)(d) Consider the testbench setup in Fig. 8.stimuliappliappligoldenmodeldesignunder testexpout(1)expout(2)out(1)out(2)acquifor k = 1:2result = true;if out(k) ~= expout(k)result = false;endendreportFigure 8: Testbench setup.i) What type of testbench is it?(1 1 / 2 )ii) The response and actual response comparison is (pseudo-)coded in the figure. (1)What is the problem with this comparison function (acqui)?iii) Briefly describe a strategy to detect such flaws in the testbench.(1)Page 13 of 30VLSI I Exam Summer 2009
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Page 8: 2 From Algorithms to Architectures
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Page 13: Problem 3: Consider the data depend
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Page 25 and 26: Problem 3: Synchronous designClkxCB
Page 27 and 28: Problem 4: Fig. 10 shows a sequenti
Page 29 and 30: Listings1 library i e e e ;2 use i
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