Sample Solution Written Exam in VLSI I - Integrated Systems ...

Problem 4: Fig. 10 shows a sequential circuit. All non zero timing parameters are marked in Fig. 10(e.g., neglect the propagation delay of the multiplexer).ClkxCRstxRBt sk,clkt sk,rstt pdt su , t hot pd c1 , t cd c1t pdt su , t hot pd c2 , t cd c2Figure 10: Sequential circuit with timing parameters.(a) Explain the additional functionality required to assure correct execution of this (3)circuit under all circumstances? Consider the circuit in Fig. 10 as a top-levelentity that is directly connected to an external quartz oscillator and reset button.Draw a block diagram of the additional functionality.Page 25 of 30VLSI I Exam Summer 2009