Sample Solution Written Exam in VLSI I - Integrated Systems ...

1 library IEEE ;2 use IEEE . std_logic_1164 . a l l ;34 entity D i g i t i s5 port ( ClkxCI : in s t d _ l o g i c ;6 RstxRBI : in s t d _ l o g i c ; −− asynchronous r e s e t ( a c t i v e low )7 I n i t x S I : in s t d _ l o g i c ; −− i n i t i a l i s e t h e BCD c onversion8 ModInxDI : in s t d _ l o g i c ; −− modulus in from l e s s s i g n i f i c a n t d i g i t9 ModOutxDO : out s t d _ l o g i c ; −− modulus out to more s i g n i f i c a n t d i g i t10 BcdOutxDO : out s t d_logic_vector (3 downto 0) −− BCD output11 ) ;12 end ;1314 architecture RTL of D i g i t i s15 signal BcdInternxDP , BcdInternxDN : std_logic_vector (3 downto 0 ) ;16 signal NextModOutxS : s t d _ l o g i c ;17 begin1819 −− C a l c u l a t e t h e s h i f t in t h e BCD r e g i s t e r . Numbers between20 −− 0 and 4 i n c l u s i v e are doubled , by s h i f t i n g by 1 .21 −− Numbers from 5 to 9 i n c l u s i v e g e t mapped to 10 , 12 , 14 ,22 −− 16 , 18. This g i v e s an modout o f 1 ( i . e . a carry to t h e23 −− next d i g i t ) , and t h e v a l u e s 0 , 2 , 4 , 6 , 8 .24 BCDdoubler : process ( BcdInternxDP , ModInxDI )25 begin26 case BcdInternxDP i s27 when " 0000 " =>28 BcdInternxDN (3 downto 1) 30 BcdInternxDN (3 downto 1) 32 BcdInternxDN (3 downto 1) 34 BcdInternxDN (3 downto 1) 36 BcdInternxDN (3 downto 1) 38 BcdInternxDN (3 downto 1) 40 BcdInternxDN (3 downto 1) 42 BcdInternxDN (3 downto 1) 44 BcdInternxDN (3 downto 1) 46 BcdInternxDN (3 downto 1) 48 BcdInternxDN (3 downto 1) ’ − ’);49 end case ;50 BcdInternxDN ( 0 )