Sample Solution Written Exam in VLSI I - Integrated Systems ...

(b) Fully parallel architecturei) The iterations can also be unrolled such that feedback loops are no longer (4)present. Draw the unrolled architecture for N=3 iterations. As before, useblocks from Fig. 5 and neglect all control signals.ii) One of the combinational blocks in the unrolled architecture can be significantlysimplified in hardware compared to the iterative implementation. Iden-(3)tify this block and give new area and propagation delay estimations for thisblock.iii) Calculate area, maximum frequency, and latency of the unrolled architecture (2)for N=3 iterations. (If the previous task was not solved, use the originalvalues for area and propagation delay of all blocks).iv) How can the throughput of the new architecture be raised 3 times without (2)large area overhead? Name the architecture transformation and describe thechanges.Page 9 of 30VLSI I Exam Summer 2009