Sample Solution Written Exam in VLSI I - Integrated Systems ...

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(c) If area efficiency is the most important goal and latency is no issue, an iterative bitserialarchitecture is the best solution. Draw a block diagram of such a CORDIC(5)architecture. Assume 8 bit word-width for all data signals and N=3 iterations.Data are fed LSB first. Use the iterative architecture as a starting point and,instead of the add/sub block, use the serial add/sub block in Fig. 6 that alreadyincludes a register for the carry-bit and its correct handling. Again, the controlsignals can be neglected.add/subrstFigure 6: Bit-serial adder(d) Bonus question: Rotation is not the only function of the CORDIC. Find a rule (2)for the calculation of d i such that z approaches the angle between the vector (x, y)and the x-axis (i.e. z → tan −1 (y/x)).Page 10 of 30VLSI I Exam Summer 2009
Problem 3: Consider the data dependency graph in Fig. 7. The input x[n] is real valued. Usef(x) = x 2 .x[n]c c c c0 1 2 3f(x)f(x) f(x) f(x)max max maxy[n]Figure 7: DDG(a) Find a mathematical expression describing the DDG above.(1)(b) A possible hardware implementation is the isomorphic architecture. Describe how (2)this architecture is obtained from a DDG.(c) How can the ’max’ operations be reordered to shorten the critical path? Which (2)algebraic property of this function is used?(d) Commutativity and distributivity of multiplications allow to reduce the total numberof multiplications in this circuit. Draw the modified(3)DDG.Page 11 of 30VLSI I Exam Summer 2009
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Page 8: 2 From Algorithms to Architectures
Page 11: (b) Fully parallel architecturei) T
Page 15 and 16: 3 Functional Verification . . . . .
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Page 21 and 22: ii) Reformulate the process stateme
Page 23 and 24: (b) What is a testbench good for? M
Page 25 and 26: Problem 3: Synchronous designClkxCB
Page 27 and 28: Problem 4: Fig. 10 shows a sequenti
Page 29 and 30: Listings1 library i e e e ;2 use i
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