Sample Solution Written Exam in VLSI I - Integrated Systems ...

More documents

Recommendations

Info

Problem 2: Verification example.Have a look at the VHDL code in Listing 1.(a) Draw an RTL block diagram, using flip-flops with active low reset, positive edgetriggeredclock input, and an enable(1 1 / 2 )signal.(b) Provide a lower bound for the number of clock cycles for exhaustive verification (2)(formula and numerical value). Does this bound hold with equality (in general)?Explain your reasoning.(c) i) Considering the inputs of the circuit, how can you reduce the verification (1)effort while still verifying most of the functionality?ii) For non-exhaustive verification in general, how can you make sure to detect (1)functional bugs?Page 14 of 30VLSI I Exam Summer 2009
(d) Draw a timing diagram with multiple clock cycles and indicate the simulation (2)events with respect to the clock signal. With an arrow, indicate the correspondenceof one data stimuli (InputxDI) application event with its response acquisition.(e) For the rest of this exercise, assume that the reset and enable signals are logicallyhigh (’1’), and can therefore be omitted.i) Draw a state transition diagram.(2)ii) Find a minimum-length input sequence to ensure exhaustive verification. (2)iii) In one sentence, formulate a general condition for exhaustive verification using (1)state-diagram terms (edges and vertices).Page 15 of 30VLSI I Exam Summer 2009
Page 4 and 5: (b) On which part of the VLSI desig
Page 6 and 7: Figure 1: An adaptive logic module
Page 8: 2 From Algorithms to Architectures
Page 11 and 12: (b) Fully parallel architecturei) T
Page 13 and 14: Problem 3: Consider the data depend
Page 15: 3 Functional Verification . . . . .
Page 19 and 20: (c) Initialization and reset mechan
Page 21 and 22: ii) Reformulate the process stateme
Page 23 and 24: (b) What is a testbench good for? M
Page 25 and 26: Problem 3: Synchronous designClkxCB
Page 27 and 28: Problem 4: Fig. 10 shows a sequenti
Page 29 and 30: Listings1 library i e e e ;2 use i
Page 31 and 32: 1 library IEEE ;2 use IEEE . std_lo

Sample Solution Written Exam in VLSI I - Integrated Systems ...

Create successful ePaper yourself

Delete template?

Save as template?