pic24fj128ga010 family - Microchip
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Note the following details of the code protection feature on <strong>Microchip</strong> devices:• <strong>Microchip</strong> products meet the specification contained in their particular <strong>Microchip</strong> Data Sheet.• <strong>Microchip</strong> believes that its <strong>family</strong> of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the <strong>Microchip</strong> products in a manner outside the operating specifications contained in <strong>Microchip</strong>’s DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.• <strong>Microchip</strong> is willing to work with the customer who is concerned about the integrity of their code.• Neither <strong>Microchip</strong> nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at <strong>Microchip</strong> are committed to continuously improving the code protection features of ourproducts. Attempts to break <strong>Microchip</strong>’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. <strong>Microchip</strong> disclaims all liabilityarising from this information and its use. Use of <strong>Microchip</strong>devices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless <strong>Microchip</strong> from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any <strong>Microchip</strong>intellectual property rights.TrademarksThe <strong>Microchip</strong> name and logo, the <strong>Microchip</strong> logo, dsPIC,KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,rfPIC and UNI/O are registered trademarks of <strong>Microchip</strong>Technology Incorporated in the U.S.A. and other countries.FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,MXDEV, MXLAB, SEEVAL and The Embedded ControlSolutions Company are registered trademarks of <strong>Microchip</strong>Technology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,ECONOMONITOR, FanSense, HI-TIDE, In-Circuit SerialProgramming, ICSP, Mindi, MiWi, MPASM, MPLAB Certifiedlogo, MPLIB, MPLINK, mTouch, Octopus, Omniscient CodeGeneration, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,PICtail, PIC 32 logo, REAL ICE, rfLAB, Select Mode, TotalEndurance, TSHARC, UniWinDriver, WiperLock and ZENAare trademarks of <strong>Microchip</strong> Technology Incorporated in theU.S.A. and other countries.SQTP is a service mark of <strong>Microchip</strong> Technology Incorporatedin the U.S.A.All other trademarks mentioned herein are property of theirrespective companies.© 2009, <strong>Microchip</strong> Technology Incorporated, Printed in theU.S.A., All Rights Reserved.Printed on recycled paper.<strong>Microchip</strong> received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and proceduresare for its PIC ® MCUs and dsPIC ® DSCs, KEELOQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, <strong>Microchip</strong>’s quality system for the designand manufacture of development systems is ISO 9001:2000 certified.DS39747E-page 2© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY64/80/100-Pin General Purpose, 16-Bit Flash MicrocontrollersHigh-Performance CPU:• Modified Harvard Architecture• Up to 16 MIPS Operation @ 32 MHz• 8 MHz Internal Oscillator with 4x PLL Option andMultiple Divide Options• 17-Bit x 17-Bit Single-Cycle HardwareMultiplier• 32-Bit by 16-Bit Hardware Divider• 16 x 16-Bit Working Register Array• C Compiler Optimized Instruction Set Architecture:- 76 base instructions- Flexible addressing modes• Two Address Generation Units for Separate Readand Write Addressing of Data MemorySpecial Microcontroller Features:• Operating Voltage Range of 2.0V to 3.6V• Flash Program Memory:- 1000 erase/write cycles- 20-year data retention minimum• Self-Reprogrammable under Software Control• Selectable Power Management modes:- Sleep, Idle and Alternate Clock modes• Fail-Safe Clock Monitor Operation:- Detects clock failure and switches to on-chip,low-power RC oscillator• On-Chip 2.5V Regulator• JTAG Boundary Scan and Programming Support• Power-on Reset (POR), Power-up Timer (PWRT)and Oscillator Start-up Timer (OST)• Flexible Watchdog Timer (WDT) with On-Chip,Low-Power RC Oscillator for Reliable Operation• In-Circuit Serial Programming (ICSP) andIn-Circuit Emulation (ICE) via 2 PinsAnalog Features:• 10-Bit, Up to 16-Channel Analog-to-Digital Converter- 500 ksps conversion rate- Conversion available during Sleep and Idle• Dual Analog Comparators with ProgrammableInput/Output ConfigurationPeripheral Features:• Two 3-Wire/4-Wire SPI modules, Supporting4 Frame modes with 8-Level FIFO Buffer• Two I 2 C modules Support Multi-Master/Slavemode and 7-Bit/10-Bit Addressing• Two UART modules:- Supports RS-232, RS-485 and LIN 1.2- On-chip hardware encoder/decoder for IrDA ®- Auto-wake-up on Start bit- Auto-Baud Detect- 4-level FIFO buffer• Parallel Master Slave Port (PMP/PSP):- Supports 8-bit or 16-bit data- Supports 16 address lines• Hardware Real-Time Clock/Calendar (RTCC):- Provides clock, calendar and alarm functions• Programmable Cyclic Redundancy Check (CRC)- User-programmable polynomial- 8/16-level FIFO buffer• Five 16-Bit Timers/Counters with ProgrammablePrescaler• Five 16-Bit Capture Inputs• Five 16-Bit Compare/PWM Outputs• High-Current Sink/Source (18 mA/18 mA) on AllI/O Pins• Configurable, Open-Drain Output on Digital I/O Pins• Up to 5 External Interrupt Sources• 5.5V Tolerant Input (digital pins only)DevicePinsProgramMemory(Bytes)SRAM(Bytes)Timers16-BitCaptureInputCompare/PWM OutputUARTSPII 2 C10-BitA/D (ch)ComparatorsPMP/PSPJTAGPIC24FJ64GA006 64 64K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ96GA006 64 96K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ128GA006 64 128K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ64GA008 80 64K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ96GA008 80 96K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ128GA008 80 128K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ64GA010 100 64K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ96GA010 100 96K 8K 5 5 5 2 2 2 16 2 Y YPIC24FJ128GA010 100 128K 8K 5 5 5 2 2 2 16 2 Y Y© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 3

PIC24FJ128GA010 FAMILYDS39747E-page 4© 2009 <strong>Microchip</strong> Technology Inc.Pin Diagrams234567891011121314151648472244242526272829303132PIC24FJXXGA00614645234342414039CN15/RD6PMRD/CN14/RD5PMWR/OC5/IC5/CN13/RD4PMBE/OC4/RD3OC3/RD2OC2/RD1PMD4/RE4PMD3/RE3PMD2/RE2PMD1/RE1RF0VCAP/VDDCORESOSCI/CN1/RC13OC1/RD0IC3/PMCS2/INT3/RD10IC2/U1CTS/INT2/RD9IC1/RTCC/INT1/RD8IC4/PMCS1/INT4/RD11OSC2/CLKO/RC15OSC1/CLKI/RC12VDDSCL1/RG2U1RTS/BCLK1/SCK1/INT0/RF6U1RX/SDI1/RF2U1TX/SDO1/RF3SDA1/RG3SOSCO/T1CK/CN0/RC14AVDDU2CTS/C1OUT/AN8/RB8PMA7/C2OUT/AN9/RB9TMS/PMA13/CVREF/AN10/RB10TDO/PMA12/AN11/RB11VDDPGC2/EMUC2/AN6/OCFA/RB6PGD2/EMUD2/AN7/RB7PMA8/U2TX/SCL2/CN18/RF5PMA9/U2RX/SDA2/CN17/RF4PMD5/RE5PMD6/RE6PMD7/RE7PMA5/SCK2/CN8/RG6VDDC1IN+/AN5/CN7/RB5C1IN-/AN4/CN6/RB4C2IN+/AN3/CN5/RB3C2IN-/AN2/SS1/CN4/RB2PMA4/SDI2/CN9/RG7PMA3/SDO2/CN10/RG8PGC1/EMUC1/VREF-/AN1/CN3/RB1PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0PMA2/SS2/CN11/RG9MCLRTCK/PMA11/AN12/RB12TDI/PMA10/AN13/RB13PMA1/U2RTS/BCLK2/AN14/RB14PMA0/AN15/OCFB/CN12/RB15PMD0/RE0RF1CN16/RD7VSSVSSVssENVREG6362615960585756545553525149503837343635331719202118AVSS6464-Pin TQFPPIC24FJXXXGA006

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 5PIC24FJ128GA010 FAMILYPin Diagrams (Continued)8079782023456789101112131415166059265640392829303132333435363738PIC24FJXXGA008171819176775857275554535251PMRD/CN14/RD5PMWR/OC5/CN13/RD4CN19/RD13IC5/RD12PMBE/OC4/RD3OC3/RD2OC2/RD1PMD2/RE2PMD1/RE1PMD0/RE0RG0PMD4/RE4PMD3/RE3RF0VCAP/VDDCORESOSCI/CN1/RC13OC1/RD0IC3/PMCS2/RD10IC2/RD9IC1/RTCC/RD8IC4/PMCS1/RD11SDA2/INT4/RA15SCL2/INT3/RA14OSC2/CLKO/RC15OSC1/CLKI/RC12VDDSCL1/RG2SCK1/INT0/RF6SDI1/RF7SDO1/RF8SDA1/RG3U1RX/RF2U1TX/RF3SOSCO/T1CK/CN0/RC14PMA6/VREF+/RA10PMA7/VREF-/RA9AVDDU2CTS/C1OUT/AN8/RB8C2OUT/AN9/RB9PMA13/CVREF/AN10/RB10PMA12/AN11/RB11VDDU1CTS/CN20/RD14U1RTS/BCLK1/CN21/RD15PGC2/EMUC2/AN6/OCFA/RB6PGD2/EMUD2/AN7/RB7PMA8/U2TX/CN18/RF5PMA9/U2RX/CN17/RF4PMD5/RE5PMD6/RE6PMD7/RE7T2CK/RC1T4CK/RC3PMA5/SCK2/CN8/RG6VDDTMS/INT1/RE8TDO/INT2/RE9C1IN+/AN5/CN7/RB5C1IN-/AN4/CN6/RB4C2IN+/AN3/CN5/RB3C2IN-/AN2/SS1/CN4/RB2PMA4/SDI2/CN9/RG7PMA3/SDO2/CN10/RG8PGC1/EMUC1/AN1/CN3/RB1PGD1/EMUD1/AN0/CN2/RB0PMA2/SS2/CN11/RG9MCLRTCK/PMA11/AN12/RB12TDI/PMA10/AN13/RB13PMA1/U2RTS/BCLK2/AN14/RB14PMA0/AN15/OCFB/CN12/RB15RG1RF1CN16/RD7CN15/RD6VSSVSSVSSENVREG757473717270696866676564636162504946484745444342412123242522AVSS80-Pin TQFPPIC24FJXXXGA008

PIC24FJ128GA010 FAMILYDS39747E-page 6© 2009 <strong>Microchip</strong> Technology Inc.Pin Diagrams (Continued))92949391908988878685848382818079782023456789101112131415166564636261605956454443424140392829303132333435363738171819212295176777271706968676675747358572423259698979927464748495554535251100PMRD/CN14/RD5PMWR/OC5/CN13/RD4CN19/RD13IC5/RD12PMBE/OC4/RD3OC3/RD2OC2/RD1RA7RA6PMD2/RE2RG13RG12RG14PMD1/RE1PMD0/RE0RG0PMD4/RE4PMD3/RE3RF0SOSCI/CN1/RC13OC1/RD0IC3/PMCS2/RD10IC2/RD9IC1/RTCC/RD8IC4/PMCS1/RD11INT4/RA15INT3/RA14OSC2/CLKO/RC15OSC1/CLKI/RC12VDDSCL1/RG2SCK1/INT0/RF6SDI1/RF7SDO1/RF8SDA1/RG3U1RX/RF2U1TX/RF3VSSSOSCO/T1CK/CN0/RC14PMA6/VREF+/RA10PMA7/VREF-/RA9AVDDAVSSC1OUT/AN8/RB8C2OUT/AN9/RB9PMA13/CVREF/AN10/RB10PMA12/AN11/RB11VDDU2CTS/RF12U2RTS/BCLK2/RF13U1CTS/CN20/RD14U1RTS/BCLK1/CN21/RD15VDDVSSPGC2/EMUC2/AN6/OCFA/RB6PGD2/EMUD2/AN7/RB7PMA8/U2TX/CN18/RF5PMA9/U2RX/CN17/RF4PMD5/RE5PMD6/RE6PMD7/RE7T2CK/RC1T3CK/RC2T4CK/RC3T5CK/RC4PMA5/SCK2/CN8/RG6VDDTMS/RA0INT1/RE8INT2/RE9C1IN+/AN5/CN7/RB5C1IN-/AN4/CN6/RB4C2IN+/AN3/CN5/RB3C2IN-/AN2/SS1/CN4/RB2PMA4/SDI2/CN9/RG7PMA3/SDO2/CN10/RG8PGC1/EMUC1/AN1/CN3/RB1PGD1/EMUD1/AN0/CN2/RB0VDDRG15PMA2/SS2/CN11/RG9MCLRPMA11/AN12/RB12PMA10/AN13/RB13PMA1/AN14/RB14PMA0/AN15/OCFB/CN12/RB15RG1RF1ENVREGCN15/RD6TDO/RA5SDA2/RA3SCL2/RA2VSSVSSVSSVCAP/VDDCORETDI/RA4TCK/RA1100-Pin TQFP5026CN16/RD7PIC24FJXXGA010PIC24FJXXXGA010

PIC24FJ128GA010 FAMILYTable of Contents1.0 Device Overview .......................................................................................................................................................................... 92.0 CPU............................................................................................................................................................................................ 213.0 Memory Organization................................................................................................................................................................. 274.0 Flash Program Memory.............................................................................................................................................................. 475.0 Resets ........................................................................................................................................................................................ 536.0 Interrupt Controller ..................................................................................................................................................................... 597.0 Oscillator Configuration .............................................................................................................................................................. 938.0 Power-Saving Features............................................................................................................................................................ 1019.0 I/O Ports ................................................................................................................................................................................... 10310.0 Timer1 ...................................................................................................................................................................................... 10511.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 10712.0 Input Capture............................................................................................................................................................................ 11313.0 Output Compare....................................................................................................................................................................... 11514.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 12115.0 Inter-Integrated Circuit (I 2 C) ................................................................................................................................................. 13116.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 13917.0 Parallel Master Port (PMP)....................................................................................................................................................... 14718.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 15719.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 16920.0 10-bit High-Speed A/D Converter............................................................................................................................................. 17321.0 Comparator Module.................................................................................................................................................................. 18322.0 Comparator Voltage Reference................................................................................................................................................ 18723.0 Special Features ...................................................................................................................................................................... 18924.0 Instruction Set Summary .......................................................................................................................................................... 19925.0 Development Support............................................................................................................................................................... 20726.0 Electrical Characteristics .......................................................................................................................................................... 21127.0 Packaging Information.............................................................................................................................................................. 225Appendix A: Revision History............................................................................................................................................................. 231Index ................................................................................................................................................................................................. 233The <strong>Microchip</strong> Web Site..................................................................................................................................................................... 237Customer Change Notification Service .............................................................................................................................................. 237Customer Support.............................................................................................................................................................................. 237Reader Response .............................................................................................................................................................................. 238Product Identification System ............................................................................................................................................................ 239© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 7

PIC24FJ128GA010 FAMILYTO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your <strong>Microchip</strong>products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• <strong>Microchip</strong>’s Worldwide Web site; http://www.microchip.com• Your local <strong>Microchip</strong> sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.DS39747E-page 8© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY1.0 DEVICE OVERVIEWThis document contains device-specific information forthe following devices:• PIC24FJ64GA006• PIC24FJ64GA008• PIC24FJ64GA010• PIC24FJ96GA006• PIC24FJ96GA008• PIC24FJ96GA010• PIC24FJ128GA006• PIC24FJ128GA008• PIC24FJ128GA010This <strong>family</strong> introduces a new line of <strong>Microchip</strong> devices:a 16-bit microcontroller <strong>family</strong> with a broad peripheralfeature set and enhanced computational performance.The PIC24FJ128GA010 <strong>family</strong> offers a new migrationoption for those high-performance applications whichmay be outgrowing their 8-bit platforms, but don’trequire the numerical processing power of a digitalsignal processor.1.1 Core Features1.1.1 16-BIT ARCHITECTURECentral to all PIC24F devices is the 16-bit modifiedHarvard architecture, first introduced with <strong>Microchip</strong>’sdsPIC ® digital signal controllers. The PIC24F CPU coreoffers a wide range of enhancements, such as:• 16-bit data and 24-bit address paths, with theability to move information between data andmemory spaces• Linear addressing of up to 8 Mbytes (programspace) and 64 Kbytes (data)• A 16-element working register array with built-insoftware stack support• A 17 x 17 hardware multiplier with support forinteger math• Hardware support for 32 by 16-bit division• An instruction set that supports multipleaddressing modes and is optimized for high-levellanguages such as ‘C’• Operational performance up to 16 MIPS1.1.2 POWER-SAVING TECHNOLOGYAll of the devices in the PIC24FJ128GA010 <strong>family</strong>incorporate a range of features that can significantlyreduce power consumption during operation. Keyitems include:• On-the-Fly Clock Switching: The device clockcan be changed under software control to theTimer1 source or the internal low-power RCoscillator during operation, allowing the user toincorporate power-saving ideas into their softwaredesigns.• Doze Mode Operation: When timing-sensitiveapplications, such as serial communications,require the uninterrupted operation of peripherals,the CPU clock speed can be selectively reduced,allowing incremental power savings withoutmissing a beat.• Instruction-Based Power-Saving Modes: Themicrocontroller can suspend all operations, orselectively shut down its core while leaving itsperipherals active, with a single instruction insoftware.1.1.3 OSCILLATOR OPTIONS ANDFEATURESAll of the devices in the PIC24FJ128GA010 <strong>family</strong> offerfive different oscillator options, allowing users a rangeof choices in developing application hardware. Theseinclude:• Two Crystal modes using crystals or ceramicresonators.• Two External Clock modes offering the option of adivide-by-2 clock output.• A Fast Internal Oscillator (FRC) with a nominal8 MHz output, which can also be divided undersoftware control to provide clock speeds as low as31 kHz.• A Phase Lock Loop (PLL) frequency multiplier,available to the external oscillator modes and theFRC oscillator, which allows clock speeds of up to32 MHz.• A separate internal RC oscillator (LPRC) with afixed 31 kHz output, which provides a low-poweroption for timing-insensitive applications.The internal oscillator block also provides a stable referencesource for the Fail-Safe Clock Monitor. Thisoption constantly monitors the main clock sourceagainst a reference signal provided by the internaloscillator and enables the controller to switch to theinternal oscillator, allowing for continued low-speedoperation or a safe application shutdown.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 9

PIC24FJ128GA010 FAMILY1.1.4 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.The consistent pinout scheme used throughout theentire <strong>family</strong> also aids in migrating to the next largerdevice. This is true when moving between devices withthe same pin count, or even jumping from 64-pin to80-pin to 100-pin devices.The PIC24F <strong>family</strong> is pin-compatible with devices in thedsPIC33 <strong>family</strong>, and shares some compatibility with thepinout schema for PIC18 and dsPIC30. This extendsthe ability of applications to grow from the relativelysimple, to the powerful and complex, yet still selectinga <strong>Microchip</strong> device.1.2 Other Special Features• Communications: The PIC24FJ128GA010<strong>family</strong> incorporates a range of serial communicationperipherals to handle a range of applicationrequirements. All devices are equipped with twoindependent UARTs with built-in IrDAencoder/decoders. There are also two independentSPI modules, and two independent I 2 Cmodules that support both Master and Slavemodes of operation.• Parallel Master/Enhanced Parallel Slave Port:One of the general purpose I/O ports can bereconfigured for enhanced parallel data communications.In this mode, the port can be configuredfor both master and slave operations, andsupports 8-bit and 16-bit data transfers with up to16 external address lines in Master modes.• Real-Time Clock/Calendar: This moduleimplements a full-featured clock and calendar withalarm functions in hardware, freeing up timerresources and program memory space for use ofthe core application.• 10-Bit A/D Converter: This module incorporatesprogrammable acquisition time, allowing for achannel to be selected and a conversion to beinitiated without waiting for a sampling period, aswell as faster sampling speeds.1.3 Details on Individual FamilyMembersDevices in the PIC24FJ128GA010 <strong>family</strong> are availablein 64-pin, 80-pin and 100-pin packages. The generalblock diagram for all devices is shown in Figure 1-1.The devices are differentiated from each other in twoways:1. Flash program memory (64 Kbytes forPIC24FJ64GA devices, 96 Kbytes forPIC24FJ96GA devices and 128 Kbytes forPIC24FJ128GA devices).2. Available I/O pins and ports (53 pins on 6 ports for64-pin devices, 69 pins on 7 ports for 80-pindevices and 84 pins on 7 ports for 100-pindevices). Note also that, since interrupt-on-changeinputs are available on every I/O pin for this <strong>family</strong>of devices, the number of CN inputs also differsbetween package sizes.All other features for devices in this <strong>family</strong> are identical.These are summarized in Table 1-1.A list of the pin features available on thePIC24FJ128GA010 <strong>family</strong> devices, sorted by function,is shown in Table 1-2. Note that this table shows the pinlocation of individual peripheral features and not howthey are multiplexed on the same pin. This informationis provided in the pinout diagrams in the beginning ofthe data sheet. Multiplexed features are sorted by thepriority given to a feature, with the highest priorityperipheral being listed first.DS39747E-page 10© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 1-1:DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILYFeaturesPIC24FJ64GA006PIC24FJ96GA006PIC24FJ128GA006PIC24FJ64GA008PIC24FJ96GA008PIC24FJ128GA008PIC24FJ64GA010PIC24FJ96GA010PIC24FJ128GA010Operating FrequencyDC – 32 MHzProgram Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128KProgram Memory (Instructions) 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032Data Memory (Bytes) 8192Interrupt Sources(Soft Vectors/NMI Traps)43(39/4)I/O Ports Ports B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, GTotal I/O Pins 53 69 84Timers:Total Number (16-bit) 532-Bit (from paired 16-bit timers) 2Input Capture Channels 5Output Compare/PWM5ChannelsInput Change Notification19 22InterruptSerial Communications:UART 2SPI (3-wire/4-wire) 2I 2 C 2Parallel CommunicationsYes(PMP/PSP)JTAG Boundary ScanYes10-Bit Analog-to-Digital Module16(input channels)Analog Comparators 2Resets (and Delays)POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration WordMismatch, Repeat instruction, Hardware Traps (PWRT, OST, PLL Lock)Instruction Set76 Base Instructions, Multiple Addressing Mode VariationsPackages 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 11

PIC24FJ128GA010 FAMILYFIGURE 1-1:PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAMInterruptControllerData BusPORTA (1)8161616RA0:RA7,RA9:RA10,RA14:15PSV & TableData AccessControl Block2323PCH PCLProgram CounterStack RepeatControl ControlLogic LogicData LatchData RAMAddressLatch161616PORTB (1)RB0:RB15Address LatchProgram MemoryRead AGUWrite AGUPORTCRC1:RC4,RC12:RC15Data LatchAddress BusEA MUXPORTD (1)24Inst LatchLiteral Data1616RD0:RD15Inst RegisterPORTE (1)OSC2/CLKOOSC1/CLKIENVREGTimingGenerationFRC/LPRCOscillatorsPrecisionBand GapReferenceVoltageRegulatorInstructionDecode &ControlControl SignalsPower-upTimerOscillatorStart-up TimerPower-onResetWatchdogTimerBrown-outReset (2)DivideSupport17x17Multiplier16 x 16W Reg Array16-Bit ALU16RE0:RE9PORTF (1)RF0:RF8,RF12:RF13PORTG (1)RG0:RG9,RG12:RG15VDDCORE/VCAPVDD, VSSMCLRTimer1Timer2/3Timer4/5RTCC10-BitADCComparatorsPMP/PSPIC1-5PWM/OC1-5CN1-22 (1)SPI1/2I2C1/2UART1/2Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.2: BOR functionality is provided when the on-board voltage regulator is enabled.DS39747E-page 12© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 1-2:FunctionPIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONSPin Number64-Pin 80-Pin 100-PinI/OInputBufferDescriptionAN0 16 20 25 I ANA A/D Analog Inputs.AN1 15 19 24 I ANAAN2 14 18 23 I ANAAN3 13 17 22 I ANAAN4 12 16 21 I ANAAN5 11 15 20 I ANAAN6 17 21 26 I ANAAN7 18 22 27 I ANAAN8 21 27 32 I ANAAN9 22 28 33 I ANAAN10 23 29 34 I ANAAN11 24 30 35 I ANAAN12 27 33 41 I ANAAN13 28 34 42 I ANAAN14 29 35 43 I ANAAN15 30 36 44 I ANAAVDD 19 25 30 P — Positive Supply for Analog Modules.AVSS 20 26 31 P — Ground Reference for Analog Modules.BCLK1 35 38 48 O — UART1 IrDA ® Baud Clock.BCLK2 29 35 39 O — UART2 IrDA ® Baud Clock.C1IN- 12 16 21 I ANA Comparator 1 Negative Input.C1IN+ 11 15 20 I ANA Comparator 1 Positive Input.C1OUT 21 27 32 O — Comparator 1 Output.C2IN- 14 18 23 I ANA Comparator 2 Negative Input.C2IN+ 13 17 22 I ANA Comparator 2 Positive Input.C2OUT 22 28 33 O — Comparator 2 Output.CLKI 39 49 63 I ANA Main Clock Input Connection.CLKO 40 50 64 O — System Clock Output.CN0 48 60 74 I ST Interrupt-on-Change Inputs.CN1 47 59 73 I STCN2 16 20 25 I STCN3 15 19 24 I STCN4 14 18 23 I STCN5 13 17 22 I STCN6 12 16 21 I STCN7 11 15 20 I STCN8 4 6 10 I STCN9 5 7 11 I STCN10 6 8 12 I STCN11 8 10 14 I STCN12 30 36 44 I STCN13 52 66 81 I STCN14 53 67 82 I STCN15 54 68 83 I STCN16 55 69 84 I STCN17 31 39 49 I STLegend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/outputI 2 C = I 2 C/SMBus input buffer© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 13

PIC24FJ128GA010 FAMILYTABLE 1-2:FunctionPIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)Pin Number64-Pin 80-Pin 100-PinI/OInputBufferDescriptionCN18 32 40 50 I ST Interrupt-on-Change Inputs.CN19 — 65 80 I STCN20 — 37 47 I STCN21 — 38 48 I STCVREF 23 29 34 O ANA Comparator Voltage Reference Output.EMUC1 15 19 24 I/O ST In-Circuit Emulator Clock Input/Output.EMUD1 16 20 25 I/O ST In-Circuit Emulator Data Input/Output.EMUC2 17 21 26 I/O ST In-Circuit Emulator Clock Input/Output.EMUD2 18 22 27 I/O ST In-Circuit Emulator Data Input/Output.ENVREG 57 71 86 I ST Enable for On-Chip Voltage Regulator.IC1 42 54 68 I ST Input Capture Inputs.IC2 43 55 69 I STIC3 44 56 70 I STIC4 45 57 71 I STIC5 52 64 79 I STINT0 35 45 55 I ST External Interrupt Inputs.INT1 42 13 18 I STINT2 43 14 19 I STINT3 44 52 66 I STINT4 45 53 67 I STMCLR 7 9 13 I ST Master Clear (Device Reset) Input. This line is broughtlow to cause a Reset.OC1 46 58 72 O — Output Compare/PWM Outputs.OC2 49 61 76 O —OC3 50 62 77 O —OC4 51 63 78 O —OC5 52 66 81 O —OCFA 17 21 26 I ST Output Compare Fault A Input.OCFB 30 36 44 I ST Output Compare Fault B Input.OSC1 39 49 63 I ANA Main Oscillator Input Connection.OSC2 40 50 64 O ANA Main Oscillator Output Connection.PGC1 15 19 24 I/O ST In-Circuit Debugger and ICSP Programming Clock.PGD1 16 20 25 I/O ST In-Circuit Debugger and ICSP Programming Data.PGC2 17 21 26 I/O ST In-Circuit Debugger and ICSP Programming Clock.PGD2 18 22 27 I/O ST In-Circuit Debugger and ICSP Programming Data.Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/outputI 2 C = I 2 C/SMBus input bufferDS39747E-page 14© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 1-2:FunctionPIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)Pin Number64-Pin 80-Pin 100-PinI/OInputBufferDescriptionPMA0 30 36 44 I/O ST/TTL Parallel Master Port Address Bit 0 Input (Buffered Slavemodes) and Output (Master modes).PMA1 29 35 43 I/O ST/TTL Parallel Master Port Address Bit 1 Input (Buffered Slavemodes) and Output (Master modes).PMA2 8 10 14 O — Parallel Master Port Address (Demultiplexed MasterPMA3 6 8 12 O — modes).PMA4 5 7 11 O —PMA5 4 6 10 O —PMA6 16 24 29 O —PMA7 22 23 28 O —PMA8 32 40 50 O —PMA9 31 39 49 O —PMA10 28 34 42 O —PMA11 27 33 41 O —PMA12 24 30 35 O —PMA13 23 29 34 O —PMBE 51 63 78 O — Parallel Master Port Byte Enable Strobe.PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address bit 14.PMCS2 44 56 70 O — Parallel Master Port Chip Select 2 Strobe/Address bit 15.PMD0 60 76 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode)PMD1 61 77 94 I/O ST/TTL or Address/Data (Multiplexed Master modes).PMD2 62 78 98 I/O ST/TTLPMD3 63 79 99 I/O ST/TTLPMD4 64 80 100 I/O ST/TTLPMD5 1 1 3 I/O ST/TTLPMD6 2 2 4 I/O ST/TTLPMD7 3 3 5 I/O ST/TTLPMRD 53 67 82 I/O ST/TTL Parallel Master Port Read Strobe.PMWR 52 66 81 I/O ST/TTL Parallel Master Port Write Strobe.Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/outputI 2 C = I 2 C/SMBus input buffer© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 15

PIC24FJ128GA010 FAMILYTABLE 1-2:FunctionPIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)Pin Number64-Pin 80-Pin 100-PinI/OInputBufferDescriptionRA0 — — 17 I/O ST PORTA Digital I/O.RA1 — — 38 I/O STRA2 — — 58 I/O STRA3 — — 59 I/O STRA4 — — 60 I/O STRA5 — — 61 I/O STRA6 — — 91 I/O STRA7 — — 92 I/O STRA9 — 23 28 I/O STRA10 — 24 29 I/O STRA14 — 52 66 I/O STRA15 — 53 67 I/O STRB0 16 20 25 I/O ST PORTB Digital I/O.RB1 15 19 24 I/O STRB2 14 18 23 I/O STRB3 13 17 22 I/O STRB4 12 16 21 I/O STRB5 11 15 20 I/O STRB6 17 21 26 I/O STRB7 18 22 27 I/O STRB8 21 27 32 I/O STRB9 22 28 33 I/O STRB10 23 29 34 I/O STRB11 24 30 35 I/O STRB12 27 33 41 I/O STRB13 28 34 42 I/O STRB14 29 35 43 I/O STRB15 30 36 44 I/O STRC1 — 4 6 I/O ST PORTC Digital I/O.RC2 — — 7 I/O STRC3 — 5 8 I/O STRC4 — — 9 I/O STRC12 39 49 63 I/O STRC13 47 59 73 I/O STRC14 48 60 74 I/O STRC15 40 50 64 I/O STLegend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/outputI 2 C = I 2 C/SMBus input bufferDS39747E-page 16© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 1-2:FunctionPIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED)Pin Number64-Pin 80-Pin 100-PinI/OInputBufferDescriptionU1CTS 43 37 47 I ST UART1 Clear to Send Input.U1RTS 35 38 48 O — UART1 Request to Send Output.U1RX 34 42 52 I ST UART1 Receive.U1TX 33 41 51 O DIG UART1 Transmit Output.U2CTS 21 27 40 I ST UART2 Clear to Send Input.U2RTS 29 35 39 O — UART2 Request to Send Output.U2RX 31 39 49 I ST UART 2 Receive Input.U2TX 32 40 50 O — UART2 Transmit Output.VDD 10, 26, 38 12, 32, 48 2, 16, 37, P — Positive Supply for Peripheral Digital Logic and I/O Pins.46, 62VDDCAP 56 70 85 P — External Filter Capacitor Connection (regulator enabled).VDDCORE 56 70 85 P — Positive Supply for Microcontroller Core Logic (regulatordisabled).VREF- 15 23 28 I ANA A/D and Comparator Reference Voltage (Low) Input.VREF+ 16 24 29 I ANA A/D and Comparator Reference Voltage (High) Input.VSS 9, 25, 41 11, 31, 51 15, 36, 45,65, 75P — Ground Reference for Logic and I/O Pins.Legend: TTL = TTL input buffer ST = Schmitt Trigger input bufferANA = Analog level input/outputI 2 C = I 2 C/SMBus input buffer© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 19

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 20© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY2.0 CPUNote:This data sheet summarizes the features ofthis group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 2. “CPU”(DS39703) in the “PIC24F Family ReferenceManual” for more information.The PIC24F CPU has a 16-bit (data) modified Harvardarchitecture with an enhanced instruction set, and a24-bit instruction word with a variable length opcodefield. The Program Counter (PC) is 23 bits wide andaddresses up to 4M instructions of user programmemory space. A single-cycle instruction prefetchmechanism is used to help maintain throughput andprovides predictable execution. All instructions executein a single cycle, with the exception of instructions thatchange the program flow, the double-word move(MOV.D) instruction and the table instructions.Overhead-free program loop constructs are supportedusing the REPEAT instructions, which are interruptibleat any point.PIC24F devices have sixteen 16-bit working registersin the programmer’s model. Each of the workingregisters can act as a data, address or address offsetregister. The 16th working register (W15) operates asa Software Stack Pointer for interrupts and calls.The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K word boundary defined by the 8-bit ProgramSpace Visibility Page (PSVPAG) register. The programto data space mapping feature lets any instructionaccess program space as if it were data space.The Instruction Set Architecture (ISA) has been significantlyenhanced beyond that of the PIC18, butmaintains an acceptable level of backward compatibility.All PIC18 instructions and addressing modes aresupported either directly or through simple macros.Many of the ISA enhancements have been driven bycompiler efficiency needs.The core supports Inherent (no operand), Relative,Literal, Memory Direct and three groups of addressingmodes. All modes support Register Direct and variousRegister Indirect modes. Each group offers up to7 addressing modes. Instructions are associated withpredefined addressing modes depending upon theirfunctional requirements.For most instructions, the core is capable of executinga data (or program data) memory read, a working register(data) read, a data memory write and a program(instruction) memory read per instruction cycle. As aresult, three-parameter instructions can be supported,allowing trinary operations (that is, A + B = C) to beexecuted in a single cycle.A high-speed, 17-bit by 17-bit multiplier has beenincluded to significantly enhance the core arithmeticcapability and throughput. The multiplier supportssigned, unsigned and Mixed mode 16-bit by 16-bit or8-bit by 8-bit integer multiplication. All multiplyinstructions execute in a single cycle.The 16-bit ALU has been enhanced with integer divideassist hardware that supports an iterative,non-restoring divide algorithm. It operates in conjunctionwith the REPEAT instruction looping mechanism,and a selection of iterative divide instructions, tosupport 32-bit (or 16-bit) divided by 16-bit integersigned and unsigned division. All divide operationsrequire 19 cycles to complete but are interruptible atany cycle boundary.The PIC24F has a vectored exception scheme with upto 8 sources of non-maskable traps and up to118 interrupt sources. Each interrupt source can beassigned to one of seven priority levels.A block diagram of the CPU is shown in Figure 2-1.2.1 Programmer’s ModelThe programmer’s model for the PIC24F is shown inFigure 2-2. All registers in the programmer’s model arememory mapped and can be manipulated directly byinstructions. A description of each register is providedin Table 2-1. All registers associated with theprogrammer’s model are memory mapped.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 21

PIC24FJ128GA010 FAMILYFIGURE 2-1:PIC24F CPU CORE BLOCK DIAGRAMPSV & TableData AccessControl BlockInterruptControllerData Bus16816162323PCH PCLProgram CounterStack LoopControl ControlLogic LogicData LatchData RAMAddressLatch162316Address LatchRAGUWAGUProgram MemoryAddress BusEA MUXData Latch24ROM Latch16 16InstructionDecode &ControlInstruction RegLiteral DataControl Signalsto Various BlocksHardwareMultiplierDivideSupport16 x 16W Register Array1616-Bit ALU16To Peripheral ModulesDS39747E-page 22© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 2-1: CPU CORE REGISTERSRegister(s) NameDescriptionW0 through W15Working Register ArrayPC23-Bit Program CounterSRALU STATUS RegisterSPLIMStack Pointer Limit Value RegisterTBLPAGTable Memory Page Address RegisterPSVPAGProgram Space Visibility Page Address RegisterRCOUNTRepeat Loop Counter RegisterCORCONCPU Control RegisterFIGURE 2-2:PROGRAMMER’S MODELDivider Working RegistersMultiplier RegistersW0 (WREG)W1W2W3W4W5W6W7W8W9W10W11W12W13W14W1515Frame PointerStack Pointer00Working/AddressRegistersSPLIM0Stack Pointer Limit22 0PC07 0TBLPAG7 0PSVPAG15 0RCOUNT15 SRHSRL 0—— — — — — — DCIPL2 1 0RA N OV Z C15 0———————————— IPL3 PSV ——Program CounterData Table Page AddressProgram Space VisibilityPage AddressRepeat Loop CounterSTATUS Register (SR)Core Control Register (CORCON)Registers or bits shadowed for PUSH.S and POP.S instructions.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 23

PIC24FJ128GA010 FAMILY2.2 CPU Control RegistersREGISTER 2-1:SR: CPU STATUS REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0— — — — — — — DCbit 15 bit 8R/W-0 (1) R/W-0 (1) R/W-0 (1) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2 (2) IPL1 (2) IPL0 (2) RA N OV Z Cbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-9 Unimplemented: Read as ‘0’bit 8DC: ALU Half Carry/Borrow bit1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)of the result occurred0 = No carry-out from the 4th or 8th low-order bit of the result has occurredbit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits (2)bit 4bit 3bit 2bit 1bit 0111 = CPU interrupt priority level is 7 (15). User interrupts disabled.110 = CPU interrupt priority level is 6 (14)101 = CPU interrupt priority level is 5 (13)100 = CPU interrupt priority level is 4 (12)011 = CPU interrupt priority level is 3 (11)010 = CPU interrupt priority level is 2 (10)001 = CPU interrupt priority level is 1 (9)000 = CPU interrupt priority level is 0 (8)RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progressN: ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)OV: ALU Overflow bit1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation0 = No overflow has occurredZ: ALU Zero bit1 = An operation which effects the Z bit has set it at some time in the past0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)C: ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurredNote 1: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.2: The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level.The value in parentheses indicates the IPL when IPL3 = 1.DS39747E-page 24© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 2-2:CORCON: CORE CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0— — — — IPL3 (1) PSV — —bit 7 bit 0Legend:C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-4 Unimplemented: Read as ‘0’bit 3 IPL3: CPU Interrupt Priority Level Status bit (1)1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or lessbit 2PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data spacebit 1-0 Unimplemented: Read as ‘0’Note 1: User interrupts are disabled when IPL3 = 1.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 25

PIC24FJ128GA010 FAMILY2.3 Arithmetic Logic Unit (ALU)The PIC24F ALU is 16 bits wide and is capable of addition,subtraction, bit shifts and logic operations. Unlessotherwise mentioned, arithmetic operations are 2’scomplement in nature. Depending on the operation, theALU may affect the values of the Carry (C), Zero (Z),Negative (N), Overflow (OV) and Digit Carry (DC)Status bits in the SR register. The C and DC Status bitsoperate as Borrow and Digit Borrow bits, respectively,for subtraction operations.The ALU can perform 8-bit or 16-bit operations,depending on the mode of the instruction that is used.Data for the ALU operation can come from the Wregister array, or data memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.The PIC24F CPU incorporates hardware support forboth multiplication and division. This includes a dedicatedhardware multiplier and support hardware for16-bit divisor division.2.3.1 MULTIPLIERThe ALU contains a high-speed, 17-bit x 17-bitmultiplier. It supports unsigned, signed or mixed signoperation in several multiplication modes:1. 16-bit x 16-bit signed2. 16-bit x 16-bit unsigned3. 16-bit signed x 5-bit (literal) unsigned4. 16-bit unsigned x 16-bit unsigned5. 16-bit unsigned x 5-bit (literal) unsigned6. 16-bit unsigned x 16-bit signed7. 8-bit unsigned x 8-bit unsigned2.3.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operation with thefollowing data sizes:1. 32-bit signed/16-bit signed divide2. 32-bit unsigned/16-bit unsigned divide3. 16-bit signed/16-bit signed divide4. 16-bit unsigned/16-bit unsigned divideThe quotient for all divide instructions ends up in W0and the remainder in W1. 16-bit signed and unsignedDIV instructions can specify any W register for both the16-bit divisor (Wn) and any W register (aligned) pair(W(m+1):Wm) for the 32-bit dividend. The divide algorithmtakes one cycle per bit of divisor, so both32-bit/16-bit and 16-bit/16-bit instructions take thesame number of cycles to execute.2.3.3 MULTI-BIT SHIFT SUPPORTThe PIC24F ALU supports both single bit andsingle-cycle, multi-bit arithmetic and logic shifts.Multi-bit shifts are implemented using a shifter block,capable of performing up to a 15-bit arithmetic rightshift, or up to a 15-bit left shift, in a single cycle. Allmulti-bit shift instructions only support Register DirectAddressing for both the operand source and resultdestination.A full summary of instructions that use the shiftoperation is provided below in Table 2-2.TABLE 2-2: INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATIONInstructionDescriptionASR Arithmetic shift right source register by one or more bits.SLShift left source register by one or more bits.LSR Logical shift right source register by one or more bits.DS39747E-page 26© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY3.0 MEMORY ORGANIZATIONAs Harvard architecture devices, PIC24F microcontrollersfeature separate program and data memoryspaces and busses. This architecture also allows thedirect access of program memory from the data spaceduring code execution.3.1 Program Address SpaceThe program address memory space ofPIC24FJ128GA010 <strong>family</strong> devices is 4M instructions.The space is addressable by a 24-bit value derived fromeither the 23-bit Program Counter (PC) during programexecution, or from table operation or data spaceremapping, as described in Section 3.3 “InterfacingProgram and Data Memory Spaces”.User access to the program memory space is restrictedto the lower half of the address range (000000h to7FFFFFh). The exception is the use of TBLRD/TBLWToperations, which use TBLPAG to permit access tothe Configuration bits and Device ID sections of theconfiguration memory space.Memory maps for the PIC24FJ128GA010 <strong>family</strong> ofdevices are shown in Figure 3-1.FIGURE 3-1:PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICESPIC24FJ64GA PIC24FJ96GA PIC24FJ128GAConfiguration Memory Space User Memory SpaceGOTO InstructionReset AddressInterrupt Vector TableReservedAlternate Vector TableUser FlashProgram Memory(22K instructions)Flash Config WordsUnimplemented(Read ‘0’s)ReservedDevice ConfigurationRegistersReservedGOTO InstructionReset AddressInterrupt Vector TableReservedAlternate Vector TableUser FlashProgram Memory(32K instructions)Flash Config WordsUnimplemented(Read ‘0’s)ReservedDevice ConfigurationRegistersReservedGOTO InstructionReset AddressInterrupt Vector TableReservedAlternate Vector TableUser FlashProgram Memory(44K instructions)Flash Config WordsUnimplemented(Read ‘0’s)ReservedDevice ConfigurationRegistersReserved000000h000002h000004h0000FEh000100h000104h0001FEh000200h00ABFEh00AC00h00FFFEh010000h0157FEh015800h7FFFFEh800000hF7FFFEhF80000hF8000EhF80010hDEVID (2)DEVID (2)DEVID (2)FEFFFEhFF0000hFFFFFEhNote:Memory areas are not shown to scale.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 27

PIC24FJ128GA010 FAMILY3.1.1 PROGRAM MEMORYORGANIZATIONThe program memory space is organized inword-addressable blocks. Although it is treated as24 bits wide, it is more appropriate to think of eachaddress of the program memory as a lower and upperword, with the upper byte of the upper word beingunimplemented. The lower word always has an evenaddress, while the upper word has an odd address(Figure 3-2).Program memory addresses are always word-alignedon the lower word, and addresses are incremented ordecremented by two during code execution. Thisarrangement also provides compatibility with datamemory space addressing and makes it possible toaccess data in the program memory space.3.1.2 HARD MEMORY VECTORSAll PIC24F devices reserve the addresses between00000h and 000200h for hard coded program executionvectors. A hardware Reset vector is provided toredirect code execution from the default value of thePC on device Reset to the actual start of code. A GOTOinstruction is programmed by the user at 000000h, withthe actual address for the start of code at 000002h.PIC24F devices also have two interrupt vector tables,located from 000004h to 0000FFh and 000100h to0001FFh. These vector tables allow each of the manydevice interrupt sources to be handled by separateISRs. A more detailed discussion of the interrupt vectortables is provided in Section 6.1 “Interrupt VectorTable”.3.1.3 FLASH CONFIGURATION WORDSIn PIC24FJ128GA010 <strong>family</strong> devices, the top twowords of on-chip program memory are reserved forconfiguration information. On device Reset, the configurationinformation is copied into the appropriateConfiguration registers. The addresses of the FlashConfiguration Word for devices in thePIC24FJ128GA010 <strong>family</strong> are shown in Table 3-1.Their location in the memory map is shown with theother memory vectors in Figure 3-1.The Configuration Words in program memory are acompact format. The actual Configuration bits aremapped in several different registers in the configurationmemory space. Their order in the Flash ConfigurationWords do not reflect a corresponding arrangement in theconfiguration space. Additional details on the deviceConfiguration Words are provided in Section 23.1“Configuration Bits”.TABLE 3-1:DeviceFLASH CONFIGURATIONWORDS FORPIC24FJ128GA010 FAMILYDEVICESProgramMemory(Words)ConfigurationWordAddressesPIC24FJ64GA 22,016 00ABFCh:00ABFEhPIC24FJ96GA 32,768 00FFFCh:00FFFEhPIC24FJ128GA 44,032 0157FCh:0157FEhFIGURE 3-2:PROGRAM MEMORY ORGANIZATIONmswAddressmost significant wordleast significant wordPC Address(lsw Address)000001h000003h000005h000007h00000000000000000000000000000000231680000000h000002h000004h000006hProgram Memory‘Phantom’ Byte(read as ‘0’)Instruction WidthDS39747E-page 28© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY3.2 Data Address SpaceNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 3. “Data Memory”(DS39717) in the “PIC24F FamilyReference Manual” for more information.The PIC24F core has a separate, 16-bit wide datamemory space, addressable as a single linear range.The data space is accessed using two Address GenerationUnits (AGUs), one each for read and write operations.The data space memory map is shown inFigure 3-3.All Effective Addresses (EAs) in the data memoryspace are 16 bits wide, and point to bytes within thedata space. This gives a data space address range of64 Kbytes, or 32K words. The lower half of the datamemory space (that is, when EA = 0) is used forimplemented memory addresses, while the upper half(EA = 1) is reserved for the Program Space Visibilityarea (see Section 3.3.3 “Reading Data fromProgram Memory Using Program Space Visibility”).PIC24FJ128GA010 <strong>family</strong> devices implement a total of8 Kbytes of data memory. Should an EA point to alocation outside of this area, an all zero word or byte willbe returned.3.2.1 DATA SPACE WIDTHThe data memory space is organized inbyte-addressable, 16-bit wide blocks. Data is aligned indata memory and registers as 16-bit words, but all dataspace EAs resolve to bytes. The Least SignificantBytes of each word have even addresses, while theMost Significant Bytes have odd addresses.FIGURE 3-3:DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICESMSBAddressMSBLSBLSBAddressImplementedData RAM0001h07FFh0801h1FFFh2001h27FFh2801hSFR SpaceData RAM0000h07FEh0800h1FFEh2000h27FEh2800hSFRSpaceNearData SpaceUnimplementedRead as ‘0’7FFFh8001h7FFFh8000hProgram SpaceVisibility AreaFFFFhFFFEhNote:Data memory areas are not shown to scale.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 29

PIC24FJ128GA010 FAMILY3.2.2 DATA MEMORY ORGANIZATIONAND ALIGNMENTTo maintain backward compatibility with PIC ® devicesand improve data space memory usage efficiency, thePIC24F instruction set supports both word and byteoperations. As a consequence of byte accessibility, alleffective address calculations are internally scaled tostep through word-aligned memory. For example, thecore recognizes that Post-Modified Register IndirectAddressing mode [Ws++] will result in a value ofWs + 1 for byte operations and Ws + 2 for wordoperations.Data byte reads will read the complete word which containsthe byte, using the LSb of any EA to determinewhich byte to select. The selected byte is placed ontothe LSB of the data path. That is, data memory and registersare organized as two parallel byte-wide entitieswith shared (word) address decode but separate writelines. Data byte writes only write to the correspondingside of the array or register which matches the byteaddress.All word accesses must be aligned to an even address.Misaligned word data fetches are not supported, socare must be taken when mixing byte and word operations,or translating from 8-bit MCU code. If amisaligned read or write is attempted, an address errortrap will be generated. If the error occurred on a read,the instruction underway is completed; if it occurred ona write, the instruction will be executed but the write willnot occur. In either case, a trap is then executed, allowingthe system and/or user to examine the machinestate prior to execution of the address Fault.All byte loads into any W register are loaded into theLeast Significant Byte. The Most Significant Byte is notmodified.A sign-extend instruction (SE) is provided to allowusers to translate 8-bit signed data to 16-bit signedvalues. Alternatively, for 16-bit unsigned data, userscan clear the MSB of any W register by executing azero-extend (ZE) instruction on the appropriateaddress.Although most instructions are capable of operating onword or byte data sizes, it should be noted that someinstructions operate only on words.3.2.3 NEAR DATA SPACEThe 8-Kbyte area between 0000h and 1FFFh isreferred to as the near data space. Locations in thisspace are directly addressable via a 13-bit absoluteaddress field within all memory direct instructions. Theremainder of the data space is addressable indirectly.Additionally, the whole data space is addressable usingMOV instructions, which support Memory DirectAddressing with a 16-bit address field.3.2.4 SFR SPACEThe first 2 Kbytes of the near data space, from 0000hto 07FFh, are primarily occupied with Special FunctionRegisters (SFRs). These are used by the PIC24F coreand peripheral modules for controlling the operation ofthe device.SFRs are distributed among the modules that they control,and are generally grouped together by module.Much of the SFR space contains unused addresses;these are read as ‘0’. A diagram of the SFR space,showing where SFRs are actually implemented, isshown in Table 3-2. Each implemented area indicatesa 32-byte region where at least one address is implementedas an SFR. A complete listing of implementedSFRs, including their addresses, is shown in Tables 3-3through 3-30.TABLE 3-2:IMPLEMENTED REGIONS OF SFR DATA SPACESFR Space Addressxx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0000h Core ICN Interrupts —100h Timers Capture — Compare — — —200h I 2 C UART SPI — — I/O300h A/D — — — — — —400h — — — — — — — —500h — — — — — — — —600h PMP RTC/Comp CRC — — — I/O700h — — System NVM/PMD — — — —Legend: — = No implemented SFRs in this blockDS39747E-page 30© 2009 <strong>Microchip</strong> Technology Inc.

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 31TABLE 3-3:CPU CORE REGISTERS MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0WREG0 0000 Working Register 0 0000WREG1 0002 Working Register 1 0000WREG2 0004 Working Register 2 0000WREG3 0006 Working Register 3 0000WREG4 0008 Working Register 4 0000WREG5 000A Working Register 5 0000WREG6 000C Working Register 6 0000WREG7 000E Working Register 7 0000WREG8 0010 Working Register 8 0000WREG9 0012 Working Register 9 0000WREG10 0014 Working Register 10 0000WREG11 0016 Working Register 11 0000WREG12 0018 Working Register 12 0000WREG13 001A Working Register 13 0000WREG14 001C Working Register 14 0000WREG15 001E Working Register 15 0800SPLIM 0020 Stack Pointer Limit xxxxPCL 002E Program Counter Low Word 0000PCH 0030 — — — — — — — — Program Counter High Byte 0000TBLPAG 0032 — — — — — — — — Table Page Address Pointer 0000PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer 0000RCOUNT 0036 Repeat Loop Counter xxxxSR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000CORCON 0044 — — — — — — — — — — — — IPL3 PSV — — 0000DISICNT 0052 — — Disable Interrupts Counter xxxxLegend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsPIC24FJ128GA010 FAMILY

DS39747E-page 32 © 2009 <strong>Microchip</strong> Technology Inc.TABLE 3-4:INTERRUPT CONTROLLER REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000IFS2 0088 — — PMPIF — — — OC5IF — IC5IF IC4IF IC3IF — — — SPI2IF SPF2IF 0000IFS3 008A — RTCIF — — — — — — — INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000IFS4 008C — — — — — — — — — — — — CRCIF U2ERIF U1ERIF — 0000IEC0 0094 — — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000IEC2 0098 — — PMPIE — — — OC5IE — IC5IE IC4IE IC3IE — — — SPI2IE SPF2IE 0000IEC3 009A — RTCIE — — — — — — — INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000IEC4 009C — — — — — — — — — — — — CRCIE U2ERIE U1ERIE — 0000IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 4444IPC3 00AA — — — — — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0044IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444IPC8 00B4 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0 0044IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 4440IPC10 00B8 — — — — — — — — — OC5IP2 OC5IP1 OC5IP0 — — — — 0040IPC11 00BA — — — — — — — — — PMPIP2 PMPIP1 PMPIP0 — — — — 0040IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440IPC13 00BE — — — — — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 0440IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — — — — — — — — 0400IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsPIC24FJ128GA010 FAMILY

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 33TABLE 3-5:ICN REGISTER MAPFileName Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AllResetsCNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000CNEN2 0062 — — — — — — — — — — CN21IE (1) CN20IE (1) CN19IE (1) CN18IE CN17IE CN16IE 0000CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000CNPU2 006A — — — — — — — — — — CN21PUE (1) CN20PUE (1) CN19PUE (1) CN18PUE CN17PUE CN16PUE 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimalNote 1: Implemented in 80-pin and 100-pin devices only.TABLE 3-6:TIMER REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TMR1 0100 Timer1 Register xxxxPR1 0102 Period Register 1 FFFFT1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000TMR2 0106 Timer2 Register xxxxTMR3HLD 0108 Timer3 Holding Register (For 32-bit timer operations only) xxxxTMR3 010A Timer3 Register xxxxPR2 010C Period Register 2 FFFFPR3 010E Period Register 3 FFFFT2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000TMR4 0114 Timer4 Register xxxxTMR5HLD 0116 Timer5 Holding Register (For 32-bit operations only) xxxxTMR5 0118 Timer5 Register xxxxPR4 011A Period Register 4 FFFFPR5 011C Period Register 5 FFFFT4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsPIC24FJ128GA010 FAMILY

DS39747E-page 34 © 2009 <strong>Microchip</strong> Technology Inc.TABLE 3-7:INPUT CAPTURE REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0IC1BUF 0140 Input 1 Capture Register xxxxIC1CON 0142 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000IC2BUF 0144 Input 2 Capture Register xxxxIC2CON 0146 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000IC3BUF 0148 Input 3 Capture Register xxxxIC3CON 014A — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000IC4BUF 014C Input 4 Capture Register xxxxIC4CON 014E — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000IC5BUF 0150 Input 5 Capture Register xxxxIC5CON 0152 — — ICSIDL — — — — — ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-8:OUTPUT COMPARE REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0OC1RS 0180 Output Compare 1 Secondary Register xxxxOC1R 0182 Output Compare 1 Register xxxxOC1CON 0184 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000OC2RS 0186 Output Compare 2 Secondary Register xxxxOC2R 0188 Output Compare 2 Register xxxxOC2CON 018A — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000OC3RS 018C Output Compare 3 Secondary Register xxxxOC3R 018E Output Compare 3 Register xxxxOC3CON 0190 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000OC4RS 0192 Output Compare 4 Secondary Register xxxxOC4R 0194 Output Compare 4 Register xxxxOC4CON 0196 — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000OC5RS 0198 Output Compare 5 Secondary Register xxxxOC5R 019A Output Compare 5 Register xxxxOC5CON 019C — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsAllResetsPIC24FJ128GA010 FAMILY

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 35TABLE 3-9:I2C1 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0I2C1RCV 0200 — — — — — — — — Receive Register 0000I2C1TRN 0202 — — — — — — — — Transmit Register 00FFI2C1BRG 0204 — — — — — — — Baud Rate Generator 0000I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000I2C1ADD 020A — — — — — — Address Register 0000I2C1MSK 020C — — — — — — Address Mask 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-10:I2C2 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0I2C2RCV 0210 — — — — — — — — Receive Register 0000I2C2TRN 0212 — — — — — — — — Transmit Register 00FFI2C2BRG 0214 — — — — — — — Baud Rate Generator 0000I2C2CON 0216 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000I2C2STAT 0218 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2CPOV D/A P S R/W RBF TBF 0000I2C2ADD 021A — — — — — — Address Register 0000I2C2MSK 021C — — — — — — Address Mask 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsAllResetsPIC24FJ128GA010 FAMILY

DS39747E-page 36 © 2009 <strong>Microchip</strong> Technology Inc.TABLE 3-11:UART1 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000U1STA 0222 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110U1TXREG 0224 — — — — — — — Transmit Register xxxxU1RXREG 0226 — — — — — — — Receive Register 0000U1BRG 0228 Baud Rate Generator Prescaler 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-12:UART2 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL 0000U2STA 0232 UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110U2TXREG 0234 — — — — — — — Transmit Register xxxxU2RXREG 0236 — — — — — — — Receive Register 0000U2BRG 0238 Baud Rate Generator Prescaler 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-13:SPI1 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000SPI1CON2 0244 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000SPI1BUF 0248 SPI1 Transmit and Receive Buffer 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-14:SPI2 REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000SPI2CON2 0264 FRMEN SPIFSD SPIFPOL — — — — — — — — — — — SPIFE SPIBEN 0000SPI2BUF 0268 SPI2 Transmit and Receive Buffer 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsAllResetsAllResetsAllResetsPIC24FJ128GA010 FAMILY

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 37TABLE 3-15:ADC REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0ADC1BUF0 0300 ADC Data Buffer 0 xxxxADC1BUF1 0302 ADC Data Buffer 1 xxxxADC1BUF2 0304 ADC Data Buffer 2 xxxxADC1BUF3 0306 ADC Data Buffer 3 xxxxADC1BUF4 0308 ADC Data Buffer 4 xxxxADC1BUF5 030A ADC Data Buffer 5 xxxxADC1BUF6 030C ADC Data Buffer 6 xxxxADC1BUF7 030E ADC Data Buffer 7 xxxxADC1BUF8 0310 ADC Data Buffer 8 xxxxADC1BUF9 0312 ADC Data Buffer 9 xxxxADC1BUFA 0314 ADC Data Buffer 10 xxxxADC1BUFB 0316 ADC Data Buffer 11 xxxxADC1BUFC 0318 ADC Data Buffer 12 xxxxADC1BUFD 031A ADC Data Buffer 13 xxxxADC1BUFE 031C ADC Data Buffer 14 xxxxADC1BUFF 031E ADC Data Buffer 15 xxxxAD1CON1 0320 ADON — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE 0000AD1CON2 0322 VCFG2 VCFG1 VCFG0 r — CSCNA — — BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000AD1CON3 0324 ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000AD1CHS 0328 CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000AD1PCFG 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000AD1CSSL 0330 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal.TABLE 3-16:PORTA REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISA 02C0 TRISA15 (1) TRISA14 (1) — — — TRISA10 (1) TRISA9 (1) — TRISA7 TRISA6 TRISA5 (2) TRISA4 (2) TRISA3 (2) TRISA2 (2) TRISA1 (2) TRISA0 (2) C6FFPORTA 02C2 RA15 (1) RA14 (1) — — — RA10 (1) RA9 (1) — RA7 RA6 RA5 (2) RA4 (2) RA3 (2) RA2 (2) RA1 (2) RA0 (2) xxxxLATA 02C4 LATA15 (1) LATA14 (1) — — — LATA10 (1) LATA9 (1) — LATA7 LATA6 LATA5 (2) LATA4 (2) LATA3 (2) LATA2 (2) LATA1 (2) LATA0 (2) xxxxODCA 06C0 ODA15 (1) ODA14 (1) — — — ODA10 (1) ODA9 (1) — ODA7 ) ODA6 ODA5 (2) ODA4 (2) ODA3 (2) ODA2 (2) ODA1 (2) ODA0 (2) 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 80-pin and 100-pin devices only.2: Implemented in 100-pin devices only.AllResetsAllResetsPIC24FJ128GA010 FAMILY

DS39747E-page 38 © 2009 <strong>Microchip</strong> Technology Inc.TABLE 3-17:PORTB REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISB 02C6 TRISB15 TRISB14 TRISB13 (1) TRISB12 (1) TRISB11 (1) TRISB10 (1) TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFFPORTB 02C8 RB15 RB14 RB13 (1) RB12 (1) RB11 (1) RB10 (1) RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxxLATB 02CA LATB15 LATB14 LATB13 (1) LATB12 (1) LATB11 (1) LATB10 (1) LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxxODCB 06C6 ODB15 ODB14 ODB13 (1) ODB12 (1) ODB11 (1) ODB10 (1) ODB9 ODB8 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devicesNote 1: Unimplemented when JTAG is enabled.TABLE 3-18:PORTC REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISC 02CC TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 (2) TRISC3 (1) TRISC2 (2) TRISC1 (1) — F01EPORTC 02CE RC15 RC14 RC13 RC12 — — — — — — — RC4 (2) RC3 (1) RC2 (2) RC1 (1) — xxxxLATC 02D0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 (2) LATC3 (1) LATC2 (2) LATC1 (1) — xxxxODCC 06CC ODC15 ODC14 ODC13 ODC12 — — — — — — — ODC4 (2) ODC3 (1) ODC2 (2) ODC1 (1) — 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 80-pin and 100-pin devices only.2: Implemented in 100-pin devices onlyTABLE 3-19:PORTD REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISD 02D2 TRISD15 (1) TRISD14 (1) TRISD13 (1) TRISD12 (1) TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFFPORTD 02D4 RD15 (1) RD14 (1) RD13 (1) RD12 (1) RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxxLATD 02D6 LATD15 (1) LATD14 (1) LATD13 (1) LATD12 (1) LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxxODCD 06D2 ODD15 (1) ODD14 (1) ODD13 (1) ODD12 (1) ODD11 ODD10 ODD9 ODD8 ODD7 ODD6 ODD5 ODD4 ODD3 ODD2 ODD1 ODD0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 80-pin and 100-pin devices only.AllResetsAllResetsAllResetsPIC24FJ128GA010 FAMILY

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 39TABLE 3-20:PORTE REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISE 02D8 — — — — — — TRISE9 (1) TRISE8 (1) TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FFPORTE 02DA — — — — — — RE9 (1) RE8 (1) RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxxLATE 02DC — — — — — — LATE9 (1) LATE8 (1) LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxxODCE 06D8 — — — — — — ODE9 (1) ODE8 (1) ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 ODE0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 80-pin and 100-pin devices only.TABLE 3-21:PORTF REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISF 02DE — — TRISF13 (1)TRISF12 (1)— — — TRISF8 (2)TRISF7 (2)AllResetsAllResetsTRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 31FFPORTF 02E0 — — RG13 (1) RG12 (1) — — — RF8 (2) RF7 (2) RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxxLATF 02E2 — — LATF13 (1) LATF12 (1) — — — LATF8 (2) LATF7 (2) LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxxODCF 06DE — — ODF13 (1) ODF12 (1) — — — ODF8 (2) ODF7 (2) ODF6 ODF5 ODF4 ODF3 ODF2 ODF1 ODF0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 100-pin devices only.2: Implemented in 80-pin and 100-pin devices only.TABLE 3-22:PORTG REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0TRISG 02E4 TRISG15 TRISG14 (1) TRISG13 (1) TRISG12 (1 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 (2) TRISG0 (2) F3CFPORTG 02E6 RG15 RG14 (1) RG13 (1) RG12 (1) — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 (2) RG0 (2) xxxxLATG 02E8 LATG15 LATG14 (1) LATG13 (1) LATG12 (1) — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 (2) LATG0 (2) xxxxODCG 06E4 ODG15 ODG14 (1) ODG13 (1) ODG12 (1) — — ODG9 ODG8 ODG7 ODG6 — — ODG3 ODG2 ODG1 (2) ODG0 (2) 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.Note 1: Implemented in 100-pin devices only.2: Implemented in 80-pin and 100-pin devices only.TABLE 3-23:PAD CONFIGURATION MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PADCFG1 02FC — — — — — — — — — — — — — — RTSECSEL PMPTTL 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices.AllResetsAllResetsPIC24FJ128GA010 FAMILY

DS39747E-page 40 © 2009 <strong>Microchip</strong> Technology Inc.TABLE 3-24:PARALLEL MASTER/SLAVE PORT REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 0000PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 0000PMADDR (1) CS2 CS1 Parallel Port Destination Address (Master modes) 00000604PMDOUT1 (1) Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000PMDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000PMAEN 060C PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 0000PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008FLegend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes.TABLE 3-25:REAL-TIME CLOCK AND CALENDAR REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0ALRMVAL 0620 Alarm Value Register Window Based on ALRMPTR xxxxALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000RTCVAL 0624 RTCC Value Register Window Based on RTCPTR xxxxRCFGCAL (1) 0626 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: RCFGCAL register Reset value dependent on type of Reset.TABLE 3-26:DUAL COMPARATOR REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POS 0000CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsAllResetsAllResetsPIC24FJ128GA010 FAMILY

© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 41TABLE 3-27:CRC REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0 0000CRCXOR 0642 CRC XOR Polynomial Register 0000CRCDAT 0644 CRC Data Input Register 0000CRCWDAT 0646 CRC Result Register 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.TABLE 3-28:SYSTEM REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0AllResetsRCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx (1)OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK — LOCK — CF — SOSCEN OSWEN xxxx (2)CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 0100OSCTUN 0748 — — — — — — — — — — TUN 0000Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: RCON register Reset values dependent on type of Reset.2: OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.TABLE 3-29:NVM REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0AllResetsNVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000 (1)NVMKEY 0766 — — — — — — — — NVMKEY 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.TABLE 3-30:PMD REGISTER MAPFile Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000PMD2 0772 — — — IC5MD IC4MD IC3MD IC2MD IC1MD — — — OC5MD OC4MD OC3MD OC2MD OC1MD 0000PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCPMD — — — — — I2C2MD — 0000Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.AllResetsAllResetsPIC24FJ128GA010 FAMILY

PIC24FJ128GA010 FAMILY3.2.5 SOFTWARE STACKIn addition to its use as a working register, the W15 registerin PIC24F devices is also used as a SoftwareStack Pointer. The pointer always points to the firstavailable free word and grows from lower to higheraddresses. It pre-decrements for stack pops andpost-increments for stack pushes, as shown inFigure 3-4. Note that for a PC push during any CALLinstruction, the MSB of the PC is zero-extended beforethe push, ensuring that the MSB is always clear.Note:The Stack Pointer Limit register (SPLIM) associatedwith the Stack Pointer sets an upper address boundaryfor the stack. SPLIM is uninitialized at Reset. As is thecase for the Stack Pointer, SPLIM is forced to ‘0’because all stack operations must be word-aligned.Whenever an EA is generated using W15 as a sourceor destination pointer, the resulting address is comparedwith the value in SPLIM. If the contents of theStack Pointer (W15) and the SPLIM register are equaland a push operation is performed, a stack error trapwill not occur. The stack error trap will occur on asubsequent push operation. Thus, for example, if it isdesirable to cause a stack error trap when the stackgrows beyond address 2000h in RAM, initialize theSPLIM with the value, 1FFEh.Similarly, a Stack Pointer underflow (stack error) trap isgenerated when the Stack Pointer address is found tobe less than 0800h. This prevents the stack frominterfering with the Special Function Register (SFR)space.A write to the SPLIM register should not be immediatelyfollowed by an indirect read operation using W15.FIGURE 3-4:0000hStack Grows TowardsHigher AddressA PC push during exception processingwill concatenate the SRL register to theMSB of the PC prior to the push.15PC000000000 PCCALL STACK FRAME0W15 (before CALL)W15 (after CALL)POP : [--W15]PUSH : [W15++]3.3 Interfacing Program and DataMemory SpacesThe PIC24F architecture uses a 24-bit wide programspace and 16-bit wide data space. The architecture isalso a modified Harvard scheme, meaning that datacan also be present in the program space. To use thisdata successfully, it must be accessed in a way thatpreserves the alignment of information in both spaces.Aside from normal execution, the PIC24F architectureprovides two methods by which program space can beaccessed during operation:• Using table instructions to access individual bytesor words anywhere in the program space• Remapping a portion of the program space intothe data space (Program Space Visibility)Table instructions allow an application to read or writeto small areas of the program memory. This makes themethod ideal for accessing data tables that need to beupdated from time to time. It also allows access to allbytes of the program word. The remapping methodallows an application to access a large block of data ona read-only basis, which is ideal for look ups from alarge table of static data. It can only access the leastsignificant word of the program word.3.3.1 ADDRESSING PROGRAM SPACESince the address ranges for the data and programspaces are 16 and 24 bits, respectively, a method isneeded to create a 23-bit or 24-bit program addressfrom 16-bit data registers. The solution depends on theinterface method to be used.For table operations, the 8-bit Table Page register(TBLPAG) is used to define a 32K word region withinthe program space. This is concatenated with a 16-bitEA to arrive at a full 24-bit program space address. Inthis format, the Most Significant bit of TBLPAG is usedto determine if the operation occurs in the user memory(TBLPAG = 0) or the configuration memory(TBLPAG = 1).For remapping operations, the 8-bit Program SpaceVisibility register (PSVPAG) is used to define a16K word page in the program space. When the MostSignificant bit of the EA is ‘1’, PSVPAG is concatenatedwith the lower 15 bits of the EA to form a 23-bit programspace address. Unlike table operations, this limitsremapping operations strictly to the user memory area.Table 3-31 and Figure 3-5 show how the program EA iscreated for table operations and remapping accessesfrom the data EA. Here, P refers to a programspace word, whereas D refers to a data spaceword.DS39747E-page 42© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 3-31:Access TypeInstruction Access(Code Execution)TBLRD/TBLWT(Byte/Word Read/Write)Program Space Visibility(Block Remap/Read)Note 1:PROGRAM SPACE ADDRESS CONSTRUCTIONAccessSpaceProgram Space Address User 0 PC 00xx xxxx xxxx xxxx xxxx xxx0User TBLPAG Data EA0xxx xxxxxxxx xxxx xxxx xxxxConfiguration TBLPAG Data EA1xxx xxxxxxxx xxxx xxxx xxxxUser 0 PSVPAG Data EA (1)0 xxxx xxxx xxx xxxx xxxx xxxxData EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 ofthe address is PSVPAG.FIGURE 3-5:DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATIONProgram Counter (1)0Program Counter023 bitsEA1/0Table Operations (2)1/0TBLPAG8 bits16 bits24 bitsSelect1EA0Program Space Visibility (1)(Remapping)0PSVPAG8 bits15 bits23 bitsUser/ConfigurationSpace SelectByte SelectNote 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment ofdata in the program and data spaces.2: Table operations are not required to be word-aligned. Table read operations are permitted in theconfiguration memory space.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 43

PIC24FJ128GA010 FAMILY3.3.2 DATA ACCESS FROM PROGRAMMEMORY USING TABLEINSTRUCTIONSThe TBLRDL and TBLWTL instructions offer a directmethod of reading or writing the lower word of anyaddress within the program space, without goingthrough data space. The TBLRDH and TBLWTH instructionsare the only method to read or write the upper 8 bitsof a program space word as data.The PC is incremented by two for each successive24-bit program word. This allows program memoryaddresses to directly map to data space addresses.Program memory can thus be regarded as two 16-bitword wide address spaces, residing side by side, eachwith the same address range. TBLRDL and TBLWTLaccess the space which contains the least significantdata word, and TBLRDH and TBLWTH access the spacewhich contains the upper data byte.Two table instructions are provided to move byte orword-sized (16-bit) data to and from program space.Both function as either byte or word operations.1. TBLRDL (Table Read Low): In Word mode, itmaps the lower word of the program spacelocation (P) to a data address (D).In Byte mode, either the upper or lower byte ofthe lower program word is mapped to the lowerbyte of a data address. The upper byte isselected when byte select is ‘1’; the lower byteis selected when it is ‘0’.2. TBLRDH (Table Read High): In Word mode, itmaps the entire upper word of a program address(P) to a data address. Note thatD, the “phantom byte”, will always be ‘0’.In Byte mode, it maps the upper or lower byte ofthe program word to D of the dataaddress, as above. Note that the data willalways be ‘0’ when the upper “phantom” byte isselected (byte select = 1).In a similar fashion, two table instructions, TBLWTHand TBLWTL, are used to write individual bytes orwords to a program space address. The details oftheir operation are explained in Section 4.0 “FlashProgram Memory”.For all table operations, the area of program memoryspace to be accessed is determined by the Table Pageregister (TBLPAG). TBLPAG covers the entire programmemory space of the device, including user and configurationspaces. When TBLPAG = 0, the Table Pageis located in the user memory space. WhenTBLPAG = 1, the page is located in configurationspace.Note:Only table read operations will execute inthe configuration memory space, and onlythen, in implemented areas such as theDevice ID. Table write operations are notallowed.FIGURE 3-6:TBLPAG02ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONSProgram SpaceData EA23 15 0000000h23 1680000000000000000020000h00000000030000h000000000‘Phantom’ ByteTBLRDH.B (Wn = 0)TBLRDL.B (Wn = 1)TBLRDL.B (Wn = 0)TBLRDL.W800000hThe address for the table operation is determined by the data EAwithin the page defined by the TBLPAG register.Only read operations are shown; write operations are also valid inthe user memory area.DS39747E-page 44© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY3.3.3 READING DATA FROM PROGRAMMEMORY USING PROGRAM SPACEVISIBILITYThe upper 32 Kbytes of data space may optionally bemapped into any 16K word page of the program space.This provides transparent access of stored constantdata from the data space without the need to usespecial instructions (i.e., TBLRDL/H).Program space access through the data space occursif the Most Significant bit of the data space EA is ‘1’ andprogram space visibility is enabled by setting the PSVbit in the Core Control register (CORCON). Thelocation of the program memory space to be mappedinto the data space is determined by the ProgramSpace Visibility Page register (PSVPAG). This 8-bitregister defines any one of 256 possible pages of16K words in program space. In effect, PSVPAG functionsas the upper 8 bits of the program memoryaddress, with the 15 bits of the EA functioning as thelower bits. Note that by incrementing the PC by 2 foreach program memory word, the lower 15 bits of dataspace addresses directly map to the lower 15 bits in thecorresponding program space addresses.Data reads to this area add an additional cycle to theinstruction being executed, since two program memoryfetches are required.Although each data space address, 8000h and higher,maps directly into a corresponding program memoryaddress (see Figure 3-7), only the lower 16 bits of the24-bit program word are used to contain the data. Theupper 8 bits of any program space locations used asdata should be programmed with ‘1111 1111’ or‘0000 0000’ to force a NOP. This prevents possibleissues should the area of code ever be accidentallyexecuted.Note:PSV access is temporarily disabled duringtable reads/writes.For operations that use PSV and are executed outsidea REPEAT loop, the MOV and MOV.D instructions willrequire one instruction cycle in addition to the specifiedexecution time. All other instructions will require twoinstruction cycles in addition to the specified executiontime.For operations that use PSV which are executed insidea REPEAT loop, there will be some instances thatrequire two instruction cycles in addition to thespecified execution time of the instruction:• Execution in the first iteration• Execution in the last iteration• Execution prior to exiting the loop due to aninterrupt• Execution upon re-entering the loop after aninterrupt is servicedAny other iteration of the REPEAT loop will allow theinstruction accessing data, using PSV, to execute in asingle cycle.FIGURE 3-7:PROGRAM SPACE VISIBILITY OPERATIONWhen CORCON = 1 and EA = 1:PSVPAG02Program Space23 15 0000000h010000h018000hData Space0000hData EAThe data in the pagedesignated byPSVPAG is mappedinto the upper half ofthe data memoryspace....8000h800000hPSV AreaFFFFh...while the lower 15bits of the EA specifyan exact addresswithin the PSV area.This correspondsexactly to the samelower 15 bits of theactual program spaceaddress.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 45

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 46© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY4.0 FLASH PROGRAM MEMORYNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 4. “ProgramMemory” (DS39715) in the “PIC24FFamily Reference Manual” for moreinformation.The PIC24FJ128GA010 <strong>family</strong> of devices containsinternal Flash program memory for storing and executingapplication code. The memory is readable, writableand erasable during normal operation over the entireVDD range.Flash memory can be programmed in four ways:1. In-Circuit Serial Programming (ICSP)2. Run-Time Self-Programming (RTSP)3. JTAG4. Enhanced In-Circuit Serial Programming(Enhanced ICSP)ICSP allows a PIC24FJ128GA010 <strong>family</strong> device to beserially programmed while in the end application circuit.This is simply done with two lines for ProgrammingClock and Programming Data (which are named PGCxand PGDx, respectively), and three other lines forpower (VDD), ground (VSS) and Master Clear (MCLR).This allows customers to manufacture boards withunprogrammed devices and then program the microcontrollerjust before shipping the product. This alsoallows the most recent firmware or a custom firmwareto be programmed.RTSP is accomplished using TBLRD (table read) andTBLWT (table write) instructions. With RTSP, the usermay write program memory data in blocks of 64 instructions(192 bytes) at a time, and erase program memoryin blocks of 512 instructions (1536 bytes) at a time.4.1 Table Instructions and FlashProgrammingRegardless of the method used, all programming ofFlash memory is done with the table read and tablewrite instructions. These allow direct read and writeaccess to the program memory space from the datamemory while the device is in normal operating mode.The 24-bit target address in the program memory isformed using the TBLPAG bits and the EffectiveAddress (EA) from a W register specified in the tableinstruction, as shown in Figure 4-1.The TBLRDL and the TBLWTL instructions are used toread or write to bits of program memory.TBLRDL and TBLWTL can access program memory inboth Word and Byte modes.The TBLRDH and TBLWTH instructions are used to reador write to bits of program memory. TBLRDHand TBLWTH can also access program memory in Wordor Byte mode.FIGURE 4-1:ADDRESSING FOR TABLE REGISTERS24 BitsUsingProgramCounter0Program Counter0Working Reg EAUsingTableInstruction1/0TBLPAG Reg8 Bits16 BitsUser/ConfigurationSpace Select24-Bit EAByteSelect© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 47

PIC24FJ128GA010 FAMILY4.2 RTSP OperationThe PIC24F Flash program memory array is organizedinto rows of 64 instructions or 192 bytes. RTSP allowsthe user to erase blocks of eight rows (512 instructions)at a time and to program one row at a time. It is alsopossible to program single words.The 8-row erase blocks and single row write blocks areedge-aligned, from the beginning of program memory,on boundaries of 1536 bytes and 192 bytes,respectively.When data is written to program memory using TBLWTinstructions, the data is not written directly to memory.Instead, data written using table writes is stored inholding latches until the programming sequence isexecuted.Any number of TBLWT instructions can be executedand a write will be successfully performed. However, 64TBLWT instructions are required to write the full row ofmemory.To ensure that no data is corrupted during a write, anyunused addresses should be programmed withFFFFFFh. This is because the holding latches reset toan unknown state, so if the addresses are left in theReset state, they may overwrite the locations on rowswhich were not rewritten.The basic sequence for RTSP programming is to set upa Table Pointer, then do a series of TBLWT instructionsto load the buffers. Programming is performed bysetting the control bits in the NVMCON register.Data can be loaded in any order and the holding registerscan be written to multiple times before performinga write operation. Subsequent writes, however, willwipe out any previous writes.Note:Writing to a location multiple times withouterasing is not recommended.All of the table write operations are single-word writes(2 instruction cycles), because only the buffers arewritten. A programming cycle is required forprogramming each row4.4 Enhanced In-Circuit SerialProgrammingEnhanced In-Circuit Serial Programming uses an onboardbootloader, known as the program executive, tomanage the programming process. Using an SPI dataframe format, the program executive can erase,program and verify program memory. See the deviceprogramming specification for more information onEnhanced ICSP4.5 Control RegistersThere are two SFRs used to read and write theprogram Flash memory: NVMCON and NVMKEY.The NVMCON register (Register 4-1) controls whichblocks are to be erased, which memory type is to beprogrammed and the start of the programming cycle.NVMKEY is a write-only register that is used for writeprotection. To start a programming or erase sequence,the user must consecutively write 55h and AAh to theNVMKEY register. Refer to Section 4.6 “ProgrammingOperations” for further details.4.6 Programming OperationsA complete programming sequence is necessary forprogramming or erasing the internal Flash in RTSPmode. During a programming or an erase operation,the processor stalls (waits) until the operation isfinished. Setting the WR bit (NVMCON) starts theoperation, and the WR bit is automatically clearedwhen the operation is finished.Configuration Word values are stored in the last twolocations of program memory. Performing a page eraseoperation on the last page of program memory clearsthese values and enables code protection. As a result,avoid performing page erase operations on the lastpage of program memory.4.3 JTAG OperationThe PIC24F <strong>family</strong> supports JTAG programming andboundary scan. Boundary scan can improve the manufacturingprocess by verifying pin to PCB connectivity.Programming can be performed with industry standardJTAG programmers supporting Serial Vector Format(SVF).DS39747E-page 48© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 4-1:NVMCON: FLASH MEMORY CONTROL REGISTERR/SO-0 (1) R/W-0 (1) R/W-0 (1) U-0 U-0 U-0 U-0 U-0WR WREN WRERR — — — — —bit 15 bit 8U-0 R/W-0 (1) U-0 U-0 R/W-0 (1) R/W-0 (1) R/W-0 (1) R/W-0 (1)— ERASE — — NVMOP3 (2) NVMOP2 (2) NVMOP1 (2) NVMOP0 (2)bit 7 bit 0Legend:SO = Settable-Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14WR: Write Control bit1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit iscleared by hardware once operation is complete.0 = Program or erase operation is complete and inactiveWREN: Write Enable bit1 = Enable Flash program/erase operations0 = Inhibit Flash program/erase operationsbit 13 WRERR: Write Sequence Error Flag bit1 = An improper program or erase sequence attempt or termination has occurred (bit is set automaticallyon any set attempt of the WR bit)0 = The program or erase operation completed normallybit 12-7 Unimplemented: Read as ‘0’bit 6ERASE: Erase/Program Enable bit1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR commandbit 5-4 Unimplemented: Read as ‘0’bit 3-0 NVMOP3:NVMOP0: NVM Operation Select bits (2)1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0) (3)0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)Note 1: These bits can only be reset on POR.2: All other combinations of NVMOP3:NVMOP0 are unimplemented.3: Available in ICSP mode only. Refer to device programming specification.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 49

PIC24FJ128GA010 FAMILY4.6.1 PROGRAMMING ALGORITHM FORFLASH PROGRAM MEMORYThe user can program one row of program Flash memoryat a time. To do this, it is necessary to erase the 8-rowerase block containing the desired row. The generalprocess is:1. Read eight rows of program memory(512 instructions) and store in data RAM.2. Update the program data in RAM with thedesired new data.3. Erase the block (see Example 4-1):a) Set the NVMOP bits (NVMCON) to‘0010’ to configure for block erase. Set theERASE (NVMCON) and WREN(NVMCON) bits.b) Write the starting address of the block to beerased into the TBLPAG and W registers.c) Write 55h to NVMKEY.d) Write AAh to NVMKEY.e) Set the WR bit (NVMCON). The erasecycle begins and the CPU stalls for the durationof the erase cycle. When the erase isdone, the WR bit is cleared automatically.4. Write the first 64 instructions from data RAM intothe program memory buffers (see Example 4-2).5. Write the program block to Flash memory:a) Set the NVMOP bits to ‘0001’ to configurefor row programming. Clear the ERASE bitand set the WREN bit.b) Write 55h to NVMKEY.c) Write AAh to NVMKEY.d) Set the WR bit. The programming cyclebegins and the CPU stalls for the duration ofthe write cycle. When the write to Flashmemory is done, the WR bit is clearedautomatically.6. Repeat steps 4 and 5, using the next available64 instructions from the block in data RAM byincrementing the value in TBLPAG, until all512 instructions are written back to Flashmemory.For protection against accidental operations, the writeinitiate sequence for NVMKEY must be used to allowany erase or program operation to proceed. After theprogramming command has been executed, the usermust wait for the programming time until programmingis complete. The two instructions following the start ofthe programming sequence should be NOPs, as shownin Example 4-3.EXAMPLE 4-1:ERASING A PROGRAM MEMORY BLOCK; Set up NVMCON for block erase operationMOV #0x4042, W0 ;MOV W0, NVMCON ; Initialize NVMCON; Init pointer to row to be ERASEDMOV #tblpage(PROG_ADDR), W0 ;MOV W0, TBLPAG ; Initialize PM Page Boundary SFRMOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA[15:0] pointerTBLWTL W0, [W0] ; Set base address of erase blockDISI #5 ; Block all interrupts with priority

PIC24FJ128GA010 FAMILYEXAMPLE 4-2:LOADING THE WRITE BUFFERS; Set up NVMCON for row programming operationsMOV #0x4001, W0 ;MOV W0, NVMCON ; Initialize NVMCON; Set up a pointer to the first program memory location to be written; program memory selected, and writes enabledMOV #0x0000, W0 ;MOV W0, TBLPAG ; Initialize PM Page Boundary SFRMOV #0x6000, W0 ; An example program memory address; Perform the TBLWT instructions to write the latches; 0th_program_wordMOV #LOW_WORD_0, W2 ;MOV #HIGH_BYTE_0, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch; 1st_program_wordMOV #LOW_WORD_1, W2 ;MOV #HIGH_BYTE_1, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch; 2nd_program_wordMOV #LOW_WORD_2, W2 ;MOV #HIGH_BYTE_2, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch•••; 63rd_program_wordMOV #LOW_WORD_31, W2 ;MOV #HIGH_BYTE_31, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0] ; Write PM high byte into program latchEXAMPLE 4-3:INITIATING A PROGRAMMING SEQUENCEDISI #5 ; Block all interrupts with priority

PIC24FJ128GA010 FAMILY4.6.2 PROGRAMMING A SINGLE WORDOF FLASH PROGRAM MEMORYIf a Flash location has been erased, it can be programmedusing table write instructions to write aninstruction word (24-bit) into the write latch. TheTBLPAG register is loaded with the 8 Most SignificantBytes of the Flash address. The TBLWTL and TBLWTHinstructions write the desired data into the write latchesand specify the lower 16 bits of the program memoryaddress to write to. To configure the NVMCON registerfor a word write, set the NVMOP bits (NVMCON)to ‘0011’. The write is performed by executing theunlock sequence and setting the WR bit.EXAMPLE 4-4:PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY; Setup a pointer to data Program MemoryMOV #tblpage(PROG_ADDR), W0 ;MOV W0, TBLPAG ;Initialize PM Page Boundary SFRMOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory addressMOV #LOW_WORD_N, W2 ;MOV #HIGH_BYTE_N, W3 ;TBLWTL W2, [W0] ; Write PM low word into program latchTBLWTH W3, [W0++] ; Write PM high byte into program latch; Setup NVMCON for programming one word to data Program MemoryMOV #0x4003, W0 ;MOV W0, NVMCON ; Set NVMOP bits to 0011DISI #5 ; Disable interrupts while the KEY sequence iswrittenMOV #0x55, W0 ; Write the key sequenceMOV W0, NVMKEYMOV #0xAA, W0MOV W0, NVMKEYBSET NVMCON, #WR ; Start the write cycleDS39747E-page 52© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY5.0 RESETSNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 7. “Reset”(DS39712) in the “PIC24F FamilyReference Manual” for more information.The Reset module combines all Reset sources andcontrols the device Master Reset Signal, SYSRST. Thefollowing is a list of device Reset sources:• POR: Power-on Reset• MCLR: Pin Reset• SWR: RESET Instruction• WDT: Watchdog Timer Reset• BOR: Brown-out Reset• CM: Configuration Word Mismatch Reset• TRAPR: Trap Conflict Reset• IOPUWR: Illegal Opcode Reset• UWR: Uninitialized W Register ResetNote:All types of device Reset will set a corresponding statusbit in the RCON register to indicate the type of Reset(see Register 5-1). A POR will clear all bits except forthe BOR and POR bits (RCON), which are set.The user may set or clear any bit at any time duringcode execution. The RCON bits only serve as statusbits. Setting a particular Reset status bit in software willnot cause a device Reset to occur.The RCON register also has other bits associated withthe Watchdog Timer and device power-saving states.The function of these bits is discussed in other sectionsof this manual.Note:Refer to the specific peripheral or CPUsection of this manual for register Resetstates.The status bits in the RCON registershould be cleared after they are read sothat the next RCON register value after adevice Reset will be meaningful.A simplified block diagram of the Reset module isshown in Figure 5-1.Any active source of Reset will make the SYSRST signalactive. Many registers associated with the CPU andperipherals are forced to a known Reset state. Mostregisters are unaffected by a Reset; their status isunknown on POR and unchanged by all other Resets.FIGURE 5-1:RESET SYSTEM BLOCK DIAGRAMRESETInstructionGlitch FilterMCLRWDTModuleSleep or IdleVDDVDD RiseDetectPORSYSRSTBrown-outResetBOREnable Voltage RegulatorTrap ConflictIllegal OpcodeUninitialized W RegisterConfiguration Word Mismatch Reset© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 53

PIC24FJ128GA010 FAMILYREGISTER 5-1: RCON: RESET CONTROL REGISTER (1)R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0TRAPR IOPUWR — — — — CM VREGSbit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1EXTR SWR SWDTEN (2) WDTO SLEEP IDLE BOR PORbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 TRAPR: Trap Reset Flag bit1 = A Trap Conflict Reset has occurred0 = A Trap Conflict Reset has not occurredbit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as anAddress Pointer caused a Reset0 = An illegal opcode or uninitialized W Reset has not occurredbit 13-10 Unimplemented: Read as ‘0’bit 9CM: Configuration Word Mismatch Reset Flag bit1 = A Configuration Word Mismatch Reset has occurred0 = A Configuration Word Mismatch Reset has not occurredbit 8VREGS: Voltage Regulator Standby Enable bit1 = Regulator remains active during Sleep0 = Regulator goes to standby during Sleepbit 7EXTR: External Reset (MCLR) Pin bit1 = A Master Clear (pin) Reset has occurred0 = A Master Clear (pin) Reset has not occurredbit 6SWR: Software Reset (Instruction) Flag bit1 = A RESET instruction has been executed0 = A RESET instruction has not been executedbit 5 SWDTEN: Software Enable/Disable of WDT bit (2)1 = WDT is enabled0 = WDT is disabledbit 4WDTO: Watchdog Timer Time-out Flag bit1 = WDT time-out has occurred0 = WDT time-out has not occurredbit 3SLEEP: Wake From Sleep Flag bit1 = Device has been in Sleep mode0 = Device has not been in Sleep modebit 2IDLE: Wake-up From Idle Flag bit1 = Device was in Idle mode0 = Device was not in Idle modebit 1BOR: Brown-out Reset Flag bit1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset.0 = A Brown-out Reset has not occurredbit 0POR: Power-on Reset Flag bit1 = A Power-on Reset has occurred0 = A Power-on Reset has not occurredNote 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does notcause a device Reset.2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of theSWDTEN bit setting.DS39747E-page 54© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 5-1: RESET FLAG BIT OPERATIONFlag Bit Setting Event Clearing EventTRAPR (RCON) Trap conflict event PORIOPUWR (RCON) Illegal opcode or uninitialized W register access POREXTR (RCON) MCLR Reset PORSWR (RCON) RESET instruction PORWDTO (RCON) WDT time-out PWRSAV instruction, PORSLEEP (RCON) PWRSAV #SLEEP instruction PORIDLE (RCON) PWRSAV #IDLE instruction PORBOR (RCON) POR, BOR —POR (RCON) POR —Note: All Reset flag bits may be set or cleared by the user software.5.1 Clock Source Selection at ResetIf clock switching is enabled, the system clock sourceat device Reset is chosen as shown in Table 5-2. Ifclock switching is disabled, the system clock source isalways selected according to the oscillator Configurationbits. Refer to 7.0 “Oscillator Configuration” forfurther details.TABLE 5-2:Reset TypePORBORMCLRWDTRSWROSCILLATOR SELECTION vs.TYPE OF RESET (CLOCKSWITCHING ENABLED)Clock Source DeterminantOscillator Configuration bits(FNOSC2:FNOSC0)COSC Control bits(OSCCON)5.2 Device Reset TimesThe Reset times for various types of device Reset aresummarized in Table 5-3. Note that the system Resetsignal, SYSRST, is released after the POR and PWRTdelay times expire.The time that the device actually begins to executecode will also depend on the system oscillator delays,which include the Oscillator Start-up Timer (OST) andthe PLL lock time. The OST and PLL lock times occurin parallel with the applicable SYSRST delay times.The FSCM delay determines the time at which theFSCM begins to monitor the system clock source afterthe SYSRST signal is released.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 55

PIC24FJ128GA010 FAMILYTABLE 5-3:RESET DELAY TIMES FOR VARIOUS DEVICE RESETSReset Type Clock Source SYSRST DelaySystem ClockDelayFSCMDelayNotesPOR EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST — — 1, 2, 3ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6BOR EC, FRC, FRCDIV, LPRC TSTARTUP + TRST — — 2, 3ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 2, 3, 5, 6XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6MCLR Any Clock TRST — — 3WDT Any Clock TRST — — 3Software Any Clock TRST — — 3Illegal Opcode Any Clock TRST — — 3Uninitialized W Any Clock TRST — — 3Trap Conflict Any Clock TRST — — 3Note 1: TPOR = Power-on Reset delay (10 μs nominal).2: TSTARTUP = TVREG (10 μs nominal) if on-chip regulator enabled or TPWRT (64 ms nominal) if on-chipregulator disabled.3: TRST = Internal state Reset time (20 μs nominal).4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing theoscillator clock to the system.5: TLOCK = PLL lock time.6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).DS39747E-page 56© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY5.2.1 POR AND LONG OSCILLATORSTART-UP TIMESThe oscillator start-up circuitry and its associated delaytimers are not linked to the device Reset delays thatoccur at power-up. Some crystal circuits (especiallylow-frequency crystals) will have a relatively longstart-up time. Therefore, one or more of the followingconditions is possible after SYSRST is released:• The oscillator circuit has not begun to oscillate.• The Oscillator Start-up Timer has NOT expired (ifa crystal oscillator is used).• The PLL has not achieved a LOCK (if PLL is used).The device will not begin to execute code until a validclock source has been released to the system. Therefore,the oscillator and PLL start-up delays must beconsidered when the Reset delay time must be known.5.2.2 FAIL-SAFE CLOCK MONITOR(FSCM) AND DEVICE RESETSIf the FSCM is enabled, it will begin to monitor the systemclock source when SYSRST is released. If a validclock source is not available at this time, the device willautomatically switch to the FRC oscillator and the usercan switch to the desired crystal oscillator in the TrapService Routine.5.3 Special Function Register ResetStatesMost of the Special Function Registers (SFRs) associatedwith the PIC24F CPU and peripherals are reset to aparticular value at a device Reset. The SFRs aregrouped by their peripheral or CPU function and theirReset values are specified in each section of this manual.The Reset value for each SFR does not depend on thetype of Reset, with the exception of four registers. TheReset value for the Reset Control register, RCON, willdepend on the type of device Reset. The Reset valuefor the Oscillator Control register, OSCCON, willdepend on the type of Reset and the programmed valuesof the oscillator Configuration bits in the FOSCDevice Configuration register (see Table 5-2). TheRCFGCAL and NVMCON registers are only affectedby a POR.5.2.2.1 FSCM Delay for Crystal and PLLClock SourcesWhen the system clock source is provided by a crystaloscillator and/or the PLL, a small delay, TFSCM, willautomatically be inserted after the POR and PWRTdelay times. The FSCM will not begin to monitor thesystem clock source until this delay expires. The FSCMdelay time is nominally 100 μs and provides additionaltime for the oscillator and/or PLL to stabilize. In mostcases, the FSCM delay will prevent an oscillator failuretrap at a device Reset when the PWRT is disabled.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 57

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 58© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY6.0 INTERRUPT CONTROLLERNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 8. “Interrupts”(DS39707) in the “PIC24F FamilyReference Manual” for more information.The PIC24F interrupt controller reduces the numerousperipheral interrupt request signals to a single interruptrequest signal to the PIC24F CPU. It has the followingfeatures:• Up to 8 processor exceptions and software traps• 7 user-selectable priority levels• Interrupt Vector Table (IVT) with up to 118 vectors• A unique vector for each interrupt or exceptionsource• Fixed priority within a specified user priority level• Alternate Interrupt Vector Table (AIVT) for debugsupport• Fixed interrupt entry and return latencies6.1 Interrupt Vector TableThe Interrupt Vector Table (IVT) is shown in Figure 6-1.The IVT resides in program memory, starting at location000004h. The IVT contains 126 vectors, consisting of8 non-maskable trap vectors, plus up to 118 sources ofinterrupt. In general, each interrupt source has its ownvector. Each interrupt vector contains a 24-bit wideaddress. The value programmed into each interrupt vectorlocation is the starting address of the associatedInterrupt Service Routine (ISR).Interrupt vectors are prioritized in terms of their naturalpriority; this is linked to their position in the vector table.All other things being equal, lower addresses have ahigher natural priority. For example, the interrupt associatedwith vector 0 will take priority over interrupts atany other vector address.PIC24FJ128GA010 <strong>family</strong> devices implement nonmaskabletraps and unique interrupts. These aresummarized in Table 6-1 and Table 6-2.6.1.1 ALTERNATE INTERRUPT VECTORTABLEThe Alternate Interrupt Vector Table (AIVT) is locatedafter the IVT as shown in Figure 6-1. Access to theAIVT is provided by the ALTIVT control bit(INTCON2). If the ALTIVT bit is set, all interruptand exception processes will use the alternate vectorsinstead of the default vectors. The alternate vectors areorganized in the same manner as the default vectors.The AIVT supports emulation and debugging efforts byproviding a means to switch between an applicationand a support environment without requiring the interruptvectors to be reprogrammed. This feature alsoenables switching between applications for evaluationof different software algorithms at run time. If the AIVTis not needed, the AIVT should be programmed withthe same addresses used in the IVT.6.2 Reset SequenceA device Reset is not a true exception because theinterrupt controller is not involved in the Reset process.The PIC24F device clears its registers in response to aReset which forces the PC to zero. The microcontrollerthen begins program execution at location 000000h.The user programs a GOTO instruction at the Resetaddress, which redirects program execution to theappropriate start-up routine.Note:Any unimplemented or unused vectorlocations in the IVT and AIVT should beprogrammed with the address of a defaultinterrupt handler routine that contains aRESET instruction.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 59

PIC24FJ128GA010 FAMILYFIGURE 6-1:PIC24F INTERRUPT VECTOR TABLEDecreasing Natural Order PriorityReset – GOTO InstructionReset – GOTO AddressReservedOscillator Fail Trap VectorAddress Error Trap VectorStack Error Trap VectorMath Error Trap VectorReservedReservedReservedInterrupt Vector 0Interrupt Vector 1———Interrupt Vector 52Interrupt Vector 53Interrupt Vector 54———Interrupt Vector 116Interrupt Vector 117ReservedReservedReservedOscillator Fail Trap VectorAddress Error Trap VectorStack Error Trap VectorMath Error Trap VectorReservedReservedReservedInterrupt Vector 0Interrupt Vector 1———Interrupt Vector 52Interrupt Vector 53Interrupt Vector 54———Interrupt Vector 116Interrupt Vector 117Start of Code000000h000002h000004h000014h00007Ch00007Eh000080h0000FCh0000FEh000100h000102h000114h00017Ch00017Eh000180h0001FEh000200hInterrupt Vector Table (IVT) (1)Alternate Interrupt Vector Table (AIVT) (1)Note 1:See Table 6-2 for the interrupt vector list.TABLE 6-1: TRAP VECTOR DETAILSVector Number IVT Address AIVT Address Trap Source0 000004h 000104h Reserved1 000006h 000106h Oscillator Failure2 000008h 000108h Address Error3 00000Ah 00010Ah Stack Error4 00000Ch 00010Ch Math Error5 00000Eh 00010Eh Reserved6 000010h 000110h Reserved7 000012h 0001172h ReservedDS39747E-page 60© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 6-2:IMPLEMENTED INTERRUPT VECTORSInterrupt SourceVectorNumberIVT AddressAIVTAddressInterrupt Bit LocationsFlag Enable PriorityADC1 Conversion Done 13 00002Eh 00012Eh IFS0 IEC0 IPC3Comparator Event 18 000038h 000138h IFS1 IEC1 IPC4CRC Generator 67 00009Ah 00019Ah IFS4 IEC4 IPC16External Interrupt 0 0 000014h 000114h IFS0 IEC0 IPC0External Interrupt 1 20 00003Ch 00013Ch IFS1 IEC1 IPC5External Interrupt 2 29 00004Eh 00014Eh IFS1 IEC1 IPC7External Interrupt 3 53 00007Eh 00017Eh IFS3 IEC3 IPC13External Interrupt 4 54 000080h 000180h IFS3 IEC3 IPC13I2C1 Master Event 17 000036h 000136h IFS1 IEC1 IPC4I2C1 Slave Event 16 000034h 000034h IFS1 IEC1 IPC4I2C2 Master Event 50 000078h 000178h IFS3 IEC3 IPC12I2C2 Slave Event 49 000076h 000176h IFS3 IEC3 IPC12Input Capture 1 1 000016h 000116h IFS0 IEC0 IPC0Input Capture 2 5 00001Eh 00011Eh IFS0 IEC0 IPC1Input Capture 3 37 00005Eh 00015Eh IFS2 IEC2 IPC9Input Capture 4 38 000060h 000160h IFS2 IEC2 IPC9Input Capture 5 39 000062h 000162h IFS2 IEC2 IPC9Input Change Notification 19 00003Ah 00013Ah IFS1 IEC1 IPC4Output Compare 1 2 000018h 000118h IFS0 IEC0 IPC0Output Compare 2 6 000020h 000120h IFS0 IEC0 IPC1Output Compare 3 25 000046h 000146h IFS1 IEC1 IPC6Output Compare 4 26 000048h 000148h IFS1 IEC1 IPC6Output Compare 5 41 000066h 000166h IFS2 IEC2 IPC10Parallel Master Port 45 00006Eh 00016Eh IFS2 IEC2 IPC11Real-Time Clock/Calendar 62 000090h 000190h IFS3 IEC3 IPC15SPI1 Error 9 000026h 000126h IFS0 IEC0 IPC2SPI1 Event 10 000028h 000128h IFS0 IEC0 IPC2SPI2 Error 32 000054h 000154h IFS2 IEC0 IPC8SPI2 Event 33 000056h 000156h IFS2 IEC2 IPC8Timer1 3 00001Ah 00011Ah IFS0 IEC0 IPC0Timer2 7 000022h 000122h IFS0 IEC0 IPC1Timer3 8 000024h 000124h IFS0 IEC0 IPC2Timer4 27 00004Ah 00014Ah IFS1 IEC1 IPC6Timer5 28 00004Ch 00014Ch IFS1 IEC1 IPC7UART1 Error 65 000096h 000196h IFS4 IEC4 IPC16UART1 Receiver 11 00002Ah 00012Ah IFS0 IEC0 IPC2UART1 Transmitter 12 00002Ch 00012Ch IFS0 IEC0 IPC3UART2 Error 66 000098h 000198h IFS4 IEC4 IPC16UART2 Receiver 30 000050h 000150h IFS1 IEC1 IPC7UART2 Transmitter 31 000052h 000152h IFS1 IEC1 IPC7© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 61

PIC24FJ128GA010 FAMILY6.3 Interrupt Control and StatusRegistersThe PIC24FJ128GA010 <strong>family</strong> devices implement atotal of 28 registers for the interrupt controller:• INTCON1• INTCON2• IFS0 through IFS4• IEC0 through IEC4• IPC0 through IPC14, and IPC16Global interrupt control functions are controlled fromINTCON1 and INTCON2. INTCON1 contains the InterruptNesting Disable (NSTDIS) bit, as well as thecontrol and status flags for the processor trap sources.The INTCON2 register controls the external interruptrequest signal behavior and the use of the AlternateInterrupt Vector Table.The IFS registers maintain all of the interrupt requestflags. Each source of interrupt has a status bit which isset by the respective peripherals, or external signal,and is cleared via software.The IEC registers maintain all of the interrupt enablebits. These control bits are used to individually enableinterrupts from the peripherals or external signals.The IPC registers are used to set the interrupt prioritylevel for each source of interrupt. Each user interruptsource can be assigned to one of eight priority levels.The interrupt sources are assigned to the IFSx, IECxand IPCx registers in the same sequence that they arelisted in Table 6-2. For example, the INT0 (ExternalInterrupt 0) is shown as having a vector number and anatural order priority of 0. Thus, the INT0IF status bit isfound in IFS0, the enable bit in IEC0 and thepriority bits in the first position of IPC0 (IPC0).Although they are not specifically part of the interruptcontrol hardware, two of the CPU control registers containbits that control interrupt functionality. The CPUSTATUS register (SR) contains the IPL2:IPL0 bits(SR). These indicate the current CPU interruptpriority level. The user may change the current CPUpriority level by writing to the IPL bits.The CORCON register contains the IPL3 bit, whichtogether with IPL2:IPL0, also indicates the current CPUpriority level. IPL3 is a read-only bit so that trap eventscannot be masked by the user software.All Interrupt registers are described in Register 6-1through Register 6-30, in the following pages.DS39747E-page 62© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-1:SR: CPU STATUS REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0— — — — — — — DC (1)bit 15 bit 8R/W-0 (1) R/W-0 (1) R/W-0 (1) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL2 (2,3) IPL1 (2,3) IPL0 (2,3) RA (1) N (1) OV (1) Z (1) C (1)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits (2,3)111 = CPU interrupt priority level is 7 (15). User interrupts disabled.110 = CPU interrupt priority level is 6 (14)101 = CPU interrupt priority level is 5 (13)100 = CPU interrupt priority level is 4 (12)011 = CPU interrupt priority level is 3 (11)010 = CPU interrupt priority level is 2 (10)001 = CPU interrupt priority level is 1 (9)000 = CPU interrupt priority level is 0 (8)Note 1: See Register 2-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions.2: The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. Thevalue in parentheses indicates the interrupt priority level if IPL3 = 1.3: The IPL Status bits are read-only when NSTDIS (INTCON1) = 1.REGISTER 6-2:CORCON: CORE CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0— — — — IPL3 (2) PSV (1) — —bit 7 bit 0Legend:C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 3 IPL3: CPU Interrupt Priority Level Status bit (2)1 = CPU interrupt priority level is greater than 70 = CPU interrupt priority level is 7 or lessNote 1: See Register 2-2 for the description of remaining bit(s) that are not dedicated to interrupt control functions.2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR) to form the CPU interrupt priority level.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 63

PIC24FJ128GA010 FAMILYREGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0NSTDIS — — — — — — —bit 15 bit 8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0— — — MATHERR ADDRERR STKERR OSCFAIL —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 NSTDIS: Interrupt Nesting Disable bit1 = Interrupt nesting is disabled0 = Interrupt nesting is enabledbit 14-5 Unimplemented: Read as ‘0’bit 4bit 3bit 2MATHERR: Arithmetic Error Trap Status bit1 = Overflow trap has occurred0 = Overflow trap has not occurredADDRERR: Address Error Trap Status bit1 = Address error trap has occurred0 = Address error trap has not occurredSTKERR: Stack Error Trap Status bit1 = Stack error trap has occurred0 = Stack error trap has not occurredbit 1OSCFAIL: Oscillator Failure Trap Status bit1 = Oscillator failure trap has occurred0 = Oscillator failure trap has not occurredbit 0 Unimplemented: Read as ‘0’DS39747E-page 64© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0ALTIVT DISI — — — — — —bit 15 bit 8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — INT4EP INT3EP INT2EP INT1EP INT0EPbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15ALTIVT: Enable Alternate Interrupt Vector Table bit1 = Use alternate vector table0 = Use standard (default) vector tablebit 14 DISI: DISI Instruction Status bit1 = DISI instruction is active0 = DISI is not activebit 13-5 Unimplemented: Read as ‘0’bit 4bit 3bit 2bit 1bit 0INT4EP: External Interrupt 4 Edge Detect Polarity Select bit1 = Interrupt on negative edge0 = Interrupt on positive edgeINT3EP: External Interrupt 3 Edge Detect Polarity Select bit1 = Interrupt on negative edge0 = Interrupt on positive edgeINT2EP: External Interrupt 2 Edge Detect Polarity Select bit1 = Interrupt on negative edge0 = Interrupt on positive edgeINT1EP: External Interrupt 1 Edge Detect Polarity Select bit1 = Interrupt on negative edge0 = Interrupt on positive edgeINT0EP: External Interrupt 0 Edge Detect Polarity Select bit1 = Interrupt on negative edge0 = Interrupt on positive edge© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 65

PIC24FJ128GA010 FAMILYREGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IFbit 15 bit 8R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 AD1IF: A/D Conversion Complete Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 10 SPI1IF: SPI1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 9SPF1IF: SPI1 Fault Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 8T3IF: Timer3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 7T2IF: Timer2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 6OC2IF: Output Compare Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 5IC2IF: Input Capture Channel 2 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 4 Unimplemented: Read as ‘0’bit 3T1IF: Timer1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 2OC1IF: Output Compare Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 1IC1IF: Input Capture Channel 1 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 0INT0IF: External Interrupt 0 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredDS39747E-page 66© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF —bit 15 bit 8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — INT1IF CNIF CMIF MI2C1IF SI2C1IFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14bit 13bit 12bit 11bit 10U2TXIF: UART2 Transmitter Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredU2RXIF: UART2 Receiver Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredINT2IF: External Interrupt 2 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredT5IF: Timer5 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredT4IF: Timer4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredOC4IF: Output Compare Channel 4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 9OC3IF: Output Compare Channel 3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 8-5 Unimplemented: Read as ‘0’bit 4bit 3bit 2bit 1bit 0INT1IF: External Interrupt 1 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredCNIF: Input Change Notification Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredCMIF: Comparator Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredMI2C1IF: Master I2C1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredSI2C1IF: Slave I2C1 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurred© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 67

PIC24FJ128GA010 FAMILYREGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0— — PMPIF — — — OC5IF —bit 15 bit 8R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0IC5IF IC4IF IC3IF — — — SPI2IF SPF2IFbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 12-10 Unimplemented: Read as ‘0’bit 9OC5IF: Output Compare Channel 5 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 8 Unimplemented: Read as ‘0’bit 7IC5IF: Input Capture Channel 5 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 6IC4IF: Input Capture Channel 4 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 5IC3IF: Input Capture Channel 3 Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 4-2 Unimplemented: Read as ‘0’bit 1SPI2IF: SPI2 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 0SPF2IF: SPI2 Fault Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredDS39747E-page 68© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0— PMPIF — — — — — —bit 15 bit 8U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0— IC4IF IC3IF — — SPI2IF SPI2IF —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 13-7 Unimplemented: Read as ‘0’bit 6INT4IF: External Interrupt 4 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 5INT3IF: External Interrupt 3 Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 4-3 Unimplemented: Read as ‘0’bit 2MI2C2IF: Master I2C2 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 1SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 69

PIC24FJ128GA010 FAMILYREGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0— — — — CRCIF U2ERIF U1ERIF —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-4 Unimplemented: Read as ‘0’bit 3CRCIF: CRC Generator Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 2U2ERIF: UART2 Error Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 1U1ERIF: UART1 Error Interrupt Flag Status bit1 = Interrupt request has occurred0 = Interrupt request has not occurredbit 0 Unimplemented: Read as ‘0’DS39747E-page 70© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IEbit 15 bit 8R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 AD1IE: A/D Conversion Complete Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 11 U1RXIE: UART1 Receiver Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 10 SPI1IE: SPI1 Transfer Complete Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 9SPF1IE: SPI1 Fault Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 8T3IE: Timer3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 7T2IE: Timer2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 6OC2IE: Output Compare Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 5IC2IE: Input Capture Channel 2 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 4 Unimplemented: Read as ‘0’bit 3T1IE: Timer1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 2OC1IE: Output Compare Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 1IC1IE: Input Capture Channel 1 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 0INT0IE: External Interrupt 0 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 71

PIC24FJ128GA010 FAMILYREGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE —bit 15 bit 8U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — INT1IE CNIE CMIE MI2C1IE SI2C1IEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14bit 13bit 12bit 11bit 10U2TXIE: UART2 Transmitter Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledU2RXIE: UART2 Receiver Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledINT2IE: External Interrupt 2 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledT5IE: Timer5 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledT4IE: Timer4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledOC4IE: Output Compare Channel 4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 9OC3IE: Output Compare Channel 3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 8-5 Unimplemented: Read as ‘0’bit 4bit 3bit 2bit 1bit 0INT1IE: External Interrupt 1 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledCNIE: Input Change Notification Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledCMIE: Comparator Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledMI2C1IE: Master I2C1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledSI2C1IE: Slave I2C1 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledDS39747E-page 72© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 U-0— — PMPIE — — — OC5IE —bit 15 bit 8R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0IC5IE IC4IE IC3IE — — — SPI2IE SPF2IEbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 PMPIE: Parallel Master Port Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 12-10 Unimplemented: Read as ‘0’bit 9OC5IE: Output Compare Channel 5 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 8 Unimplemented: Read as ‘0’bit 7IC5IE: Input Capture Channel 5 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 6IC4IE: Input Capture Channel 4 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 5IC3IE: Input Capture Channel 3 Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 4-2 Unimplemented: Read as ‘0’bit 1SPI2IE: SPI2 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 0SPF2IE: SPI2 Fault Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabled© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 73

PIC24FJ128GA010 FAMILYREGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0— RTCIE — — — — — —bit 15 bit 8U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0— INT4IE INT3IE — — MI2C2IE SI2C2IE —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 13-7 Unimplemented: Read as ‘0’bit 6INT4IE: External Interrupt 4 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 5INT3IE: External Interrupt 3 Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 4-3 Unimplemented: Read as ‘0’bit 2MI2C2IE: Master I2C2 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 1SI2C2IE: Slave I2C2 Event Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 0 Unimplemented: Read as ‘0’DS39747E-page 74© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0— — — — CRCIE U2ERIE U1ERIE —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-4 Unimplemented: Read as ‘0’bit 3CRCIE: CRC Generator Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 2U2ERIE: UART2 Error Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 1U1ERIE: UART1 Error Interrupt Enable bit1 = Interrupt request enabled0 = Interrupt request not enabledbit 0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 75

PIC24FJ128GA010 FAMILYREGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 T1IP2:T1IP0: Timer1 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledDS39747E-page 76© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— IC2IP2 IC2IP1 IC2IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 T2IP2:T2IP0: Timer2 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 77

PIC24FJ128GA010 FAMILYREGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledDS39747E-page 78© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-7 Unimplemented: Read as ‘0’bit 6-4 AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabled© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 79

PIC24FJ128GA010 FAMILYREGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 MI2C1IP2:MI2C1IP0: Master I2C1 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 SI2C1IP2:SI2C1IP0: Slave I2C1 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledDS39747E-page 80© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0— — — — — INT1IP2 INT1IP1 INT1IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-3 Unimplemented: Read as ‘0’bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabled© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 81

PIC24FJ128GA010 FAMILYREGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— OC3IP2 OC3IP1 OC3IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 T4IP2:T4IP0: Timer4 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’DS39747E-page 82© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 INT2IP2:INT2IP0: External Interrupt 2 Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabled© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 83

PIC24FJ128GA010 FAMILYREGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— SPI2IP2 SPI2IP1 SPI2IP0 — SPF2IP2 SPF2IP1 SPF2IP0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-7 Unimplemented: Read as ‘0’bit 6-4 SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3 Unimplemented: Read as ‘0’bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledDS39747E-page 84© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— IC3IP2 IC3IP1 IC3IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 85

PIC24FJ128GA010 FAMILYREGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— OC5IP2 OC5IP1 OC5IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-7 Unimplemented: Read as ‘0’bit 6-4 OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’REGISTER 6-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— PMPIP2 PMPIP1 PMPIP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-7 Unimplemented: Read as ‘0’bit 6-4 PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’DS39747E-page 86© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0— — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-11 Unimplemented: Read as ‘0’bit 10-8 MI2C2IP2:MI2C2IP0: Master I2C2 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 SI2C2IP2:SI2C2IP0: Slave I2C2 Event Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 87

PIC24FJ128GA010 FAMILYREGISTER 6-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0— — — — — INT4IP2 IN4IP1 INT4IP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— INT3IP2 INT3IP1 INT3IP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-11 Unimplemented: Read as ‘0’bit 10-8 INT4IP2:INT4IP0: External Interrupt 4 Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 INT3IP2:INT3IP0: External Interrupt 3 Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’DS39747E-page 88© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 6-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0— — — — — RTCIP2 RTCIP1 RTCIP0bit 15 bit 8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-11 Unimplemented: Read as ‘0’bit 10-8 RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7-0 Unimplemented: Read as ‘0’© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 89

PIC24FJ128GA010 FAMILYREGISTER 6-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0— CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0bit 15 bit 8U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0— U1ERIP2 U1ERIP1 U1ERIP0 — — — —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 11 Unimplemented: Read as ‘0’bit 10-8 U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 7 Unimplemented: Read as ‘0’bit 6-4 U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits111 = Interrupt is priority 7 (highest priority interrupt)•••001 = Interrupt is priority 1000 = Interrupt source is disabledbit 3-0 Unimplemented: Read as ‘0’DS39747E-page 90© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY6.4 Interrupt Setup Procedures6.4.1 INITIALIZATIONTo configure an interrupt source:1. Set the NSTDIS Control bit (INTCON1) ifnested interrupts are not desired.2. Select the user-assigned priority level for theinterrupt source by writing the control bits in theappropriate IPCx Control register. The prioritylevel will depend on the specific application andtype of interrupt source. If multiple priority levelsare not desired, the IPCx register control bits forall enabled interrupt sources may beprogrammed to the same non-zero value.Note:At a device Reset, the IPC registers areinitialized, such that all user interruptsources are assigned to priority level 4.3. Clear the interrupt flag status bit associated withthe peripheral in the associated IFSx Statusregister.4. Enable the interrupt source by setting the interruptenable control bit associated with thesource in the appropriate IECx Control register.6.4.3 TRAP SERVICE ROUTINEA Trap Service Routine (TSR) is coded like an ISR,except that the appropriate trap status flag in theINTCON1 register must be cleared to avoid re-entryinto the TSR.6.4.4 INTERRUPT DISABLEAll user interrupts can be disabled using the followingprocedure:1. Push the current SR value onto the softwarestack using the PUSH instruction.2. Force the CPU to priority level 7 by inclusiveORing the value OEh with SRL.To enable user interrupts, the POP instruction may beused to restore the previous SR value.Note that only user interrupts with a priority level of 7 orless can be disabled. Trap sources (level 8-15) cannotbe disabled.The DISI instruction provides a convenient way to disableinterrupts of priority levels 1-6 for a fixed period oftime. Level 7 interrupt sources are not disabled by theDISI instruction.6.4.2 INTERRUPT SERVICE ROUTINEThe method that is used to declare an ISR and initializethe IVT with the correct vector address will depend onthe programming language (i.e., ‘C’ or assembler) andthe language development toolsuite that is used todevelop the application. In general, the user must clearthe interrupt flag in the appropriate IFSx register for thesource of interrupt that the ISR handles. Otherwise, theISR will be re-entered immediately after exiting the routine.If the ISR is coded in assembly language, it mustbe terminated using a RETFIE instruction to unstackthe saved PC value, SRL value and old CPU prioritylevel.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 91

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 92© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY7.0 OSCILLATORCONFIGURATIONNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 6. “Oscillator”(DS39700) in the “PIC24F FamilyReference Manual” for more information.The oscillator system for PIC24FJ128GA010 <strong>family</strong>devices has the following features:• A total of four external and internal oscillator optionsas clock sources, providing 11 different clock modes• On-chip 4x PLL to boost internal operating frequencyon select internal and external oscillator sources• Software-controllable switching between variousclock sources• Software-controllable postscaler for selectiveclocking of CPU for system power savings• A Fail-Safe Clock Monitor (FSCM) that detectsclock failure and permits safe application recoveryor shutdownA simplified diagram of the oscillator system is shownin Figure 7-1.FIGURE 7-1:PIC24FJ128GA010 FAMILY CLOCK DIAGRAMPrimary OscillatorPIC24FJ128GA010 FamilyCLKOOSC1XT, HS, ECCLKDIVOSC28 MHz/4 MHz4 x PLLXTPLL, HSPLL,ECPLL, FRCPLLPostscalerCPUFRCOscillator8 MHz(Nominal)PostscalerFRCDIVPeripheralsCLKDIVFRCLPRCOscillator31 kHz (Nominal)LPRCSOSCOSOSCISecondary OscillatorSOSCENEnableOscillatorSOSCClock Control LogicFail-SafeClockMonitorWDT, PWRTClock Source Optionfor Other Modules© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 93

PIC24FJ128GA010 FAMILY7.1 CPU Clocking SchemeThe system clock source can be provided by one offour sources:• Primary Oscillator (POSC) on the OSC1 andOSC2 pins• Secondary Oscillator (SOSC) on the SOSCI andSOSCO pins• Fast Internal RC (FRC) Oscillator• Low-Power Internal RC (LPRC) OscillatorThe primary oscillator and FRC sources have theoption of using the internal 4x PLL. The frequency ofthe FRC clock source can optionally be reduced by theprogrammable clock divider. The selected clock sourcegenerates the processor and peripheral clock sources.The processor clock source is divided by two to producethe internal instruction cycle clock, FCY. In thisdocument, the instruction cycle clock is also denotedby FOSC/2. The internal instruction cycle clock, FOSC/2,can be provided on the OSC2 I/O pin for someoperating modes of the primary oscillator.7.2 Oscillator Configurationsettings are located in the Configuration registers in theprogram memory (refer to Section 23.1 “ConfigurationBits” for further details.) The Primary OscillatorConfiguration bits, POSCMD1:POSCMD0(Configuration Word 2), and the Initial OscillatorSelect Configuration bits, FNOSC2:FNOSC0(Configuration Word 2), select the oscillatorsource that is used at a Power-on Reset. The FRCprimary oscillator with postscaler (FRCDIV) is thedefault (unprogrammed) selection. The secondaryoscillator, or one of the internal oscillators, may bechosen by programming these bit locations.The Configuration bits allow users to choose betweenthe various clock modes, shown in Table 7-1.7.2.1 CLOCK SWITCHING MODECONFIGURATION BITSThe FCKSM Configuration bits (Configuration Word 2)are used to jointly configure device clock switching andthe Fail-Safe Clock Monitor (FSCM). Clock switching isenabled only when FCKSM1 is programmed (‘0’). TheFSCM is enabled only when FCKSM1:FCKSM0 areboth programmed (‘00’).The oscillator source (and operating mode) that is usedat a device Power-on Reset event is selected using Configurationbit settings. The oscillator Configuration bitTABLE 7-1:CONFIGURATION BIT VALUES FOR CLOCK SELECTIONOscillator ModeOscillator SourcePOSCMD1:POSCMD0FNOSC2:FNOSC0Fast RC Oscillator with PostscalerInternal 11 111 1, 2(FRCDIV)(Reserved) Internal xx 110 1Low-Power RC Oscillator (LPRC) Internal 11 101 1Secondary (Timer1) OscillatorSecondary 11 100 1(SOSC)Primary Oscillator (HS) with PLLPrimary 10 011Module (HSPLL)Primary Oscillator (XT) with PLLPrimary 01 011Module (XTPLL)Primary Oscillator (EC) with PLLPrimary 00 011Module (ECPLL)Primary Oscillator (HS) Primary 10 010Primary Oscillator (XT) Primary 01 010Primary Oscillator (EC) Primary 00 010Fast RC Oscillator with PLL Module Internal 11 001 1(FRCPLL)Fast RC Oscillator (FRC) Internal 11 000 1Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.2: This is the default oscillator mode for an unprogrammed (erased) device.NoteDS39747E-page 94© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY7.3 Control RegistersThe operation of the oscillator is controlled by threeSpecial Function Registers:• OSCCON• CLKDIV• OSCTUNThe OSCCON register (Register 7-1) is the main controlregister for the oscillator. It controls clock sourceswitching, and allows the monitoring of clock sources.The Clock Divider register (Register 7-2) controls thefeatures associated with Doze mode, as well as thepostscaler for the FRC oscillator.The FRC Oscillator Tune register (Register 7-3) allowsthe user to fine tune the FRC oscillator over a range ofapproximately ±12%. Each bit increment or decrementchanges the factory calibrated frequency of the FRCoscillator by a fixed amount.REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTERU-0 R-0 R-0 R-0 U-0 R/W-x (1) R/W-x (1) R/W-x (1)— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0bit 15 bit 8R/SO-0 U-0 R-0 (2) U-0 R/CO-0 U-0 R/W-0 R/W-0CLKLOCK — LOCK — CF — SOSCEN OSWENbit 7 bit 0Legend: CO = Clearable-Only bit SO = Settable-Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 COSC2:COSC0: Current Oscillator Selection bits111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)bit 11 Unimplemented: Read as ‘0’bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)bit 7CLKLOCK: Clock Selection Lock Enabled bitIf FSCM is enabled (FCKSM1 = 1):1 = Clock and PLL selections are locked0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bitIf FSCM is disabled (FCKSM1 = 0):Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.bit 6 Unimplemented: Read as ‘0’Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 95

PIC24FJ128GA010 FAMILYREGISTER 7-1:OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)bit 5LOCK: PLL Lock Status bit1 = PLL module is in lock or PLL module start-up timer is satisfied0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabledbit 4 Unimplemented: Read as ‘0’bit 3CF: Clock Fail Detect bit1 = FSCM has detected a clock failure0 = No clock failure has been detectedbit 2 Unimplemented: Read as ‘0’bit 1bit 0SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit1 = Enable secondary oscillator0 = Disable secondary oscillatorOSWEN: Oscillator Switch Enable bit1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits0 = Oscillator switch is completeNote 1: Reset values for these bits are determined by the FNOSC Configuration bits.2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected.DS39747E-page 96© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 7-2:CLKDIV: CLOCK DIVIDER REGISTERR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1ROI DOZE2 DOZE1 DOZE0 DOZEN (1) RCDIV2 RCDIV1 RCDIV0bit 15 bit 8U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 7 bit 0Legend: CO = Clearable-Only bit SO = Settable-Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15ROI: Recover on Interrupt bit1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:10 = Interrupts have no effect on the DOZEN bitbit 14-12 DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits111 = 1:128110 = 1:64101 = 1:32100 = 1:16011 = 1:8010 = 1:4001 = 1:2000 = 1:1bit 11 DOZEN: DOZE Enable bit (1)1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio0 = CPU peripheral clock ratio set to 1:1bit 10-8 RCDIV2:RCDIV0: FRC Postscaler Select bits111 = 31.25 kHz (divide by 256)110 = 125 kHz (divide by 64)101 = 250 kHz (divide by 32)100 = 500 kHz (divide by 16)011 = 1 MHz (divide by 8)010 = 2 MHz (divide by 4)001 = 4 MHz (divide by 2)000 = 8 MHz (divide by 1)bit 7-0 Unimplemented: Read as ‘0’Note 1:This bit is automatically cleared when the ROI bit is set and an interrupt occurs.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 97

PIC24FJ128GA010 FAMILYREGISTER 7-3:OSCTUN: FRC OSCILLATOR TUNE REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-6 Unimplemented: Read as ‘0’bit 5-0 TUN5:TUN0: FRC Oscillator Tuning bits011111 = Maximum frequency deviation011110 =•••000001 =000000 = Center frequency, oscillator is running at factory calibrated frequency111111 =•••100001 =100000 = Minimum frequency deviationDS39747E-page 98© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY7.4 Clock Switching OperationWith few limitations, applications are free to switchbetween any of the four clock sources (POSC, SOSC,FRC and LPRC) under software control and at anytime. To limit the possible side effects that could resultfrom this flexibility, PIC24F devices have a safeguardlock built into the switching process.Note: Primary oscillator mode has threedifferent submodes (XT, HS and EC)which are determined by the POSCMDConfiguration bits. While an applicationcan switch to and from primary oscillatormode in software, it cannot switchbetween the different primary submodeswithout reprogramming the device.7.4.1 ENABLING CLOCK SWITCHINGTo enable clock switching, the FCKSM1 Configuration bitin the Flash Configuration Word 2 register must be programmedto ‘0’. (Refer to Section 23.1 “ConfigurationBits” for further details.) If the FCKSM1 Configuration bitis unprogrammed (‘1’), the clock switching function andFail-Safe Clock Monitor function are disabled. This is thedefault setting.The NOSC control bits (OSCCON) do notcontrol the clock selection when clock switching is disabled.However, the COSC bits (OSCCON)will reflect the clock source selected by the FNOSCConfiguration bits.The OSWEN control bit (OSCCON) has no effectwhen clock switching is disabled. It is held at ‘0’ at alltimes.7.4.2 OSCILLATOR SWITCHINGSEQUENCEAt a minimum, performing a clock switch requires thisbasic sequence:1. If desired, read the COSC bits(OSCCON), to determine the currentoscillator source.2. Perform the unlock sequence to allow a write tothe OSCCON register high byte.3. Write the appropriate value to the NOSC controlbits (OSCCON) for the new oscillatorsource.4. Perform the unlock sequence to allow a write tothe OSCCON register low byte.5. Set the OSWEN bit to initiate the oscillatorswitch.Once the basic sequence is completed, the systemclock hardware responds automatically as follows:1. The clock switching hardware compares theCOSC status bits with the new value of theNOSC control bits. If they are the same, then theclock switch is a redundant operation. In thiscase, the OSWEN bit is cleared automaticallyand the clock switch is aborted.2. If a valid clock switch has been initiated, theLOCK (OSCCON) and CF (OSCCON)status bits are cleared.3. The new oscillator is turned on by the hardwareif it is not currently running. If a crystal oscillatormust be turned on, the hardware will wait untilthe OST expires. If the new source is using thePLL, then the hardware waits until a PLL lock isdetected (LOCK = 1).4. The hardware waits for 10 clock cycles from thenew clock source and then performs the clockswitch.5. The hardware clears the OSWEN bit to indicate asuccessful clock transition. In addition, the NOSCbit values are transferred to the COSC status bits.6. The old clock source is turned off at this time,with the exception of LPRC (if WDT or FSCMare enabled) or SOSC (if SOSCEN remainsset).Note 1: The processor will continue to executecode throughout the clock switchingsequence. Timing sensitive code shouldnot be executed during this time.2: Direct clock switches between anyprimary oscillator mode with PLL andFRCPLL mode are not permitted. Thisapplies to clock switches in either direction.In these instances, the applicationmust switch to FRC mode as a transitionclock source between the two PLLmodes.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 99

PIC24FJ128GA010 FAMILYA recommended code sequence for a clock switchincludes the following:1. Disable interrupts during the OSCCON registerunlock and write sequence.2. Execute the unlock sequence for the OSCCONhigh byte, by writing 78h and 9Ah toOSCCON in two back-to-backinstructions.3. Write new oscillator source to the NOSC controlbits in the instruction immediately following theunlock sequence.4. Execute the unlock sequence for the OSCCONlow byte by writing 46h and 57h toOSCCON in two back-to-back instructions.5. Set the OSWEN bit in the instruction immediatelyfollowing the unlock sequence.6. Continue to execute code that is not clocksensitive (optional).7. Invoke an appropriate amount of software delay(cycle counting) to allow the selected oscillatorand/or PLL to start and stabilize.8. Check to see if OSWEN is ‘0’. If it is, the switchwas successful. If OSWEN is still set, thencheck the LOCK bit to determine cause offailure.The core sequence for unlocking the OSCCON registerand initiating a clock switch is shown in Example 7-1.EXAMPLE 7-1:BASIC CODE SEQUENCEFOR CLOCK SWITCHING;Place the new oscillator selection in W0;OSCCONH (high byte) Unlock SequenceMOV#OSCCONH, w1MOV#0x78, w2MOV#0x9A, w3MOV.b w2, [w1]MOV.b w3, [w1];Set new oscillator selectionMOV.b WREG, OSCCONH;OSCCONL (low byte) unlock sequenceMOV#OSCCONL, w1MOV#0x46, w2MOV#0x57, w3MOV.b w2, [w1]MOV.b w3, [w1];Start oscillator switch operationBSET OSCCON, #0DS39747E-page 100© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY8.0 POWER-SAVING FEATURESNote:This data sheet summarizes the features ofthis group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 10. Power-Saving Features” (DS39698) in the“PIC24F Family Reference Manual” formore information.The PIC24FJ128GA010 <strong>family</strong> of devices provide theability to manage power consumption by selectivelymanaging clocking to the CPU and the peripherals. Ingeneral, a lower clock frequency and a reduction in thenumber of circuits being clocked constitutes lowerconsumed power. All PIC24F devices manage powerconsumption in four different ways:• Clock Frequency• Instruction-Based Sleep and Idle modes• Software-Controlled Doze mode• Selective Peripheral Control in SoftwareCombinations of these methods can be used to selectivelytailor an application’s power consumption, whilestill maintaining critical application features, such astiming sensitive communications.8.1 Clock Frequency and ClockSwitchingPIC24F devices allow for a wide range of clockfrequencies to be selected under application control. Ifthe system clock configuration is not locked, users canchoose low-power or high-precision oscillators by simplychanging the NOSC bits. The process of changing a systemclock during operation, as well as limitations to theprocess, are discussed in more detail in Section 7.0“Oscillator Configuration”.Note:SLEEP_MODE and IDLE_MODE are constantsdefined in the assembler includefile for the selected device.8.2.1 SLEEP MODESleep mode has these features:• The system clock source is shut down. If anon-chip oscillator is used, it is turned off.• The device current consumption will be reducedto a minimum provided that no I/O pin is sourcingcurrent.• The Fail-Safe Clock Monitor does not operateduring Sleep mode since the system clock sourceis disabled.• The LPRC clock will continue to run in Sleepmode if the WDT is enabled.• The WDT, if enabled, is automatically clearedprior to entering Sleep mode.• Some device features or peripherals maycontinue to operate in Sleep mode. This includesitems such as the input change notification on theI/O ports, or peripherals that use an external clockinput. Any peripheral that requires the systemclock source for its operation will be disabled inSleep mode.The device will wake-up from Sleep mode on any of thethese events:• On any interrupt source that is individuallyenabled• On any form of device Reset• On a WDT time-outOn wake-up from Sleep, the processor will restart withthe same clock source that was active when Sleepmode was entered.8.2 Instruction-Based Power-SavingModesPIC24F devices have two special power-saving modesthat are entered through the execution of a specialPWRSAV instruction. Sleep mode stops clock operationand halts all code execution; Idle mode halts the CPUand code execution, but allows peripheral modules tocontinue operation. The assembly syntax of thePWRSAV instruction is shown in Example 8-1.Sleep and Idle modes can be exited as a result of anenabled interrupt, WDT time-out or a device Reset.When the device exits these modes, it is said to“wake-up”.EXAMPLE 8-1:PWRSAV INSTRUCTION SYNTAXPWRSAV #SLEEP_MODE ; Put the device into SLEEP modePWRSAV #IDLE_MODE ; Put the device into IDLE mode© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 101

PIC24FJ128GA010 FAMILY8.2.2 IDLE MODEIdle mode has these features:• The CPU will stop executing instructions.• The WDT is automatically cleared.• The system clock source remains active. Bydefault, all peripheral modules continue to operatenormally from the system clock source, but canalso be selectively disabled (see Section 8.4“Selective Peripheral Module Control”).• If the WDT or FSCM is enabled, the LPRC willalso remain active.The device will wake from Idle mode on any of theseevents:• Any interrupt that is individually enabled.• Any device Reset.• A WDT time-out.On wake-up from Idle, the clock is re-applied to theCPU and instruction execution begins immediately,starting with the instruction following the PWRSAVinstruction, or the first instruction in the ISR.8.2.3 INTERRUPTS COINCIDENT WITHPOWER SAVE INSTRUCTIONSAny interrupt that coincides with the execution of aPWRSAV instruction will be held off until entry into Sleepor Idle mode has completed. The device will thenwake-up from Sleep or Idle mode.8.3 Doze ModeGenerally, changing clock speed and invoking one ofthe power-saving modes are the preferred strategiesfor reducing power consumption. There may be circumstances,however, where this is not practical. Forexample, it may be necessary for an application tomaintain uninterrupted synchronous communication,even while it is doing nothing else. Reducing systemclock speed may introduce communication errors,while using a power-saving mode may stopcommunications completely.Doze mode is a simple and effective alternative methodto reduce power consumption while the device is stillexecuting code. In this mode, the system clock continuesto operate from the same source and at the samespeed. Peripheral modules continue to be clocked at thesame speed, while the CPU clock speed is reduced.Synchronization between the two clock domains ismaintained, allowing the peripherals to access the SFRswhile the CPU executes code at a slower rate.Doze mode is enabled by setting the DOZEN bit(CLKDIV). The ratio between peripheral and coreclock speed is determined by the DOZE2:DOZE0 bits(CLKDIV). There are eight possibleconfigurations, from 1:1 to 1:256, with 1:1 being thedefault.It is also possible to use Doze mode to selectivelyreduce power consumption in event driven applications.This allows clock sensitive functions, such assynchronous communications, to continue withoutinterruption while the CPU idles, waiting for somethingto invoke an interrupt routine. Enabling the automaticreturn to full-speed CPU operation on interrupts isenabled by setting the ROI bit (CLKDIV). Bydefault, interrupt events have no effect on Doze modeoperation.8.4 Selective Peripheral ModuleControlIdle and Doze modes allow users to substantiallyreduce power consumption by slowing or stopping theCPU clock. Even so, peripheral modules still remainclocked and thus consume power. There may be caseswhere the application needs what these modes do notprovide: the allocation of power resources to CPUprocessing with minimal power consumption from theperipherals.PIC24F devices address this requirement by allowingperipheral modules to be selectively disabled, reducingor eliminating their power consumption. This can bedone with two control bits:• The Peripheral Enable bit, generically named“XXXEN”, located in the module’s main controlSFR.• The Peripheral Module Disable (PMD) bit, genericallynamed “XXXMD”, located in one of the PMDcontrol registers.Both bits have similar functions in enabling or disablingits associated module. Setting the PMD bit for a moduledisables all clock sources to that module, reducing itspower consumption to an absolute minimum. In thisstate, the control and status registers associated with theperipheral will also be disabled, so writes to those registerswill have no effect and read values will be invalid.Many peripheral modules have a corresponding PMDbit.In contrast, disabling a module by clearing its XXXENbit disables its functionality, but leaves its registersavailable to be read and written to. Power consumptionis reduced, but not by as much as the PMD bit does.Most peripheral modules have an enable bit;exceptions include Capture, Compare and RTCC.To achieve more selective power savings, peripheralmodules can also be selectively disabled when thedevice enters Idle mode. This is done through thecontrol bit of the generic name format “XXXIDL”. Bydefault, all modules that can operate during Idle modewill do so. Using the disable on Idle feature allows furtherreduction of power consumption during Idle mode,enhancing power savings for extremely critical powerapplications.DS39747E-page 102© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY9.0 I/O PORTSNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 12. “I/O Portswith Peripheral Pin Select (PPS)”(DS39711) in the “PIC24F FamilyReference Manual” for more information.All of the device pins (except VDD, VSS, MCLR andOSC1/CLKI) are shared between the peripherals andthe parallel I/O ports. All I/O input ports feature SchmittTrigger inputs for improved noise immunity.9.1 Parallel I/O (PIO) PortsA parallel I/O port that shares a pin with a peripheral is,in general, subservient to the peripheral. The peripheral’soutput buffer data and control signals areprovided to a pair of multiplexers. The multiplexersselect whether the peripheral or the associated porthas ownership of the output data and control signals ofthe I/O pin. The logic also prevents “loop through”, inwhich a port’s digital output can drive the input of aperipheral that shares the same pin. Figure 9-1 showshow ports are shared with other peripherals and theassociated I/O pin to which they are connected.When a peripheral is enabled and the peripheral isactively driving an associated pin, the use of the pin asa general purpose output pin is disabled. The I/O pinmay be read, but the output driver for the parallel portbit will be disabled. If a peripheral is enabled, but theperipheral is not actively driving a pin, that pin may bedriven by a port.All port pins have three registers directly associatedwith their operation as digital I/O. The data directionregister (TRISx) determines whether the pin is an inputor an output. If the data direction bit is a ‘1’, then the pinis an input. All port pins are defined as inputs after aReset. Reads from the latch (LATx), read the latch.Writes to the latch, write the latch. Reads from the port(PORTx), read the port pins, while writes to the portpins, write the latch.Any bit and its associated data and control registersthat are not valid for a particular device will bedisabled. That means the corresponding LATx andTRISx registers and the port pin will read as zeros.When a pin is shared with another peripheral or functionthat is defined as an input only, it is neverthelessregarded as a dedicated port because there is noother competing source of outputs. An example is theINT4 pin.FIGURE 9-1:BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTUREPeripheral ModulePeripheral Input DataOutput MultiplexersPeripheral Module EnablePeripheral Output EnablePeripheral Output Data10Output EnableI/ORead TRISPIO Module10Output DataData BusDQI/O PinWR TRISCKTRIS LatchDQWR LAT +WR PORTCKData LatchRead LATInput DataRead PORT© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 103

PIC24FJ128GA010 FAMILY9.1.1 OPEN-DRAIN CONFIGURATIONIn addition to the PORT, LAT and TRIS registers fordata control, each port pin can also be individually configuredfor either digital or open-drain output. This iscontrolled by the Open-Drain Control register, ODCx,associated with each port. Setting any of the bits configuresthe corresponding pin to act as an open-drainoutput.The open-drain feature allows the generation ofoutputs higher than VDD (e.g., 5V) on any desired digital-onlypins by using external pull-up resistors. Themaximum open-drain voltage allowed is the same asthe maximum VIH specification.9.2 Configuring Analog Port PinsThe use of the AD1PCFG and TRIS registers controlthe operation of the A/D port pins. The port pins that aredesired as analog inputs must have their correspondingTRIS bit set (input). If the TRIS bit is cleared (output),the digital output level (VOH or VOL) will beconverted.When reading the PORT register, all pins configured asanalog input channels will read as cleared (a low level).Pins configured as digital inputs will not convert ananalog input. Analog levels on any pin that is defined asa digital input (including the ANx pins) may cause theinput buffer to consume current that exceeds thedevice specifications.9.2.1 I/O PORT WRITE/READ TIMINGOne instruction cycle is required between a portdirection change or port write operation and a readoperation of the same port. Typically this instructionwould be a NOP.9.3 Input Change NotificationThe input change notification function of the I/O portsallows the PIC24FJ128GA010 <strong>family</strong> of devices to generateinterrupt requests to the processor in response toa change-of-state on selected input pins. This featureis capable of detecting input change-of-states even inSleep mode, when the clocks are disabled. Dependingon the device pin count, there are up to 22 external signals(CN0 through CN21) that may be selected(enabled) for generating an interrupt request on achange-of-state.There are four control registers associated with the CNmodule. The CNEN1 and CNEN2 registers contain theinterrupt enable control bits for each of the CN inputpins. Setting any of these bits enables a CN interruptfor the corresponding pins.Each CN pin also has a weak pull-up connected to it.The pull-ups act as a current source that is connectedto the pin, and eliminate the need for external resistorswhen push button or keypad devices are connected.The pull-ups are enabled separately using the CNPU1and CNPU2 registers, which contain the control bits foreach of the CN pins. Setting any of the control bitsenables the weak pull-ups for the corresponding pins.When the internal pull-up is selected, the pin usesVDDCORE as the pull-up source voltage. Make sure thatthere is no external pull-up source when the internalpull-ups are enabled, as the voltage difference cancause a current path.Note:Pull-ups on change notification pinsshould always be disabled whenever theport pin is configured as a digital output.EXAMPLE 9-1: PORT WRITE/READ EXAMPLEMOV 0xFF00, W0 ; Configure PORTB as inputsMOV W0, TRISBB ; and PORTB as outputsNOP; Delay 1 cyclebtss PORTB, #13 ; Next InstructionDS39747E-page 104© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY10.0 TIMER1Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 14. “Timers”(DS39704) in the “PIC24F FamilyReference Manual” for more information.The Timer1 module is a 16-bit timer which can serve asthe time counter for the Real-Time Clock, or operate asa free-running interval timer/counter. Timer1 canoperate in three modes:• 16-Bit Timer• 16-Bit Synchronous Counter• 16-Bit Asynchronous CounterTimer1 also supports these features:• Timer gate operation• Selectable prescaler settings• Timer operation during CPU Idle and Sleepmodes• Interrupt on 16-bit Period register match or fallingedge of external gate signalFigure 10-1 presents a block diagram of the 16-bittimer module.To configure Timer1 for operation:1. Set the TON bit (= 1).2. Select the timer prescaler ratio using theTCKPS1:TCKPS0 bits.3. Set the Clock and Gating modes using the TCSand TGATE bits.4. Set or clear the TSYNC bit to configuresynchronous or asynchronous operation.5. Load the timer period value into the PR1register.6. If interrupts are required, set the interrupt enablebit, T1IE. Use the priority bits, T1IP2:T1IP0, toset the interrupt priority.FIGURE 10-1:16-BIT TIMER1 MODULE BLOCK DIAGRAMTCKPS1:TCKPS0SOSCO/T1CK1xTON2SOSCENGateSync01Prescaler1, 8, 64, 256SOSCITCY00TGATETGATETCSSet T1IF10QQDCKResetTMR101SyncEqualComparatorTSYNCPR1© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 105

PIC24FJ128GA010 FAMILYREGISTER 10-1:T1CON: TIMER1 CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON — TSIDL — — — — —bit 15 bit 8U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0— TGATE TCKPS1 TCKPS0 — TSYNC TCS —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 TON: Timer1 On bit1 = Starts 16-bit Timer10 = Stops 16-bit Timer1bit 14 Unimplemented: Read as ‘0’bit 13 TSIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-7 Unimplemented: Read as ‘0’bit 6TGATE: Timer1 Gated Time Accumulation Enable bitWhen TCS = 1:This bit is ignored.When TCS = 0:1 = Gated time accumulation enabled0 = Gated time accumulation disabledbit 5-4 TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits11 = 1:25610 = 1:6401 = 1:800 = 1:1bit 3 Unimplemented: Read as ‘0’bit 2TSYNC: Timer1 External Clock Input Synchronization Select bitWhen TCS = 1:1 = Synchronize external clock input0 = Do not synchronize external clock inputWhen TCS = 0:This bit is ignored.bit 1TCS: Timer1 Clock Source Select bit1 = External clock from pin T1CK (on the rising edge)0 = Internal clock (FOSC/2)bit 0 Unimplemented: Read as ‘0’DS39747E-page 106© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY11.0 TIMER2/3 AND TIMER4/5Note:The Timer2/3 and Timer4/5 modules are 32-bit timers,which can also be configured as four independent 16-bittimers with selectable operating modes.As a 32-bit timer, Timer2/3 and Timer4/5 operate inthree modes:• Two independent 16-bit timers (Timer2 andTimer3) with all 16-bit operating modes• Single 32-bit Timer• Single 32-bit Synchronous CounterThey also support these features:• Timer gate operation• Selectable prescaler settings• Timer operation during Idle and Sleep modes• Interrupt on a 32-bit Period register match• ADC Event Trigger (Timer4/5 only)Individually, all four of the 16-bit timers can function assynchronous timers or counters. They also offer thefeatures listed above, except for the ADC EventTrigger; this is implemented only with Timer5. Theoperating modes and enabled features are determinedby setting the appropriate bit(s) in the T2CON, T3CON,T4CON and T5CON registers. T2CON and T4CON areshown in generic form in Register 11-1; T3CON andT5CON are shown in Register 11-2.For 32-bit timer/counter operation, Timer2 and Timer4are the least significant word; Timer3 and Timer4 arethe most significant word of the 32-bit timers.Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 14. “Timers”(DS39704) in the “PIC24F FamilyReference Manual” for more information.For 32-bit operation, T3CON and T5CONcontrol bits are ignored. Only T2CON andT4CON control bits are used for setup andcontrol. Timer2 and Timer4 clock and gateinputs are utilized for the 32-bit timermodules, but an interrupt is generated withthe Timer3 or Timer5 interrupt flags.To configure Timer2/3 or Timer4/5 for 32-bit operation:1. Set the T32 bit (T2CON or T4CON = 1).2. Select the prescaler ratio for Timer2 or Timer4using the TCKPS1:TCKPS0 bits.3. Set the Clock and Gating modes using the TCSand TGATE bits.4. Load the timer period value. PR3 (or PR5) willcontain the most significant word of the value,while PR2 (or PR4) contains the least significantword.5. If interrupts are required, set the interrupt enablebit, T3IE or T5IE; use the priority bits,T3IP2:T3IP0 or T5IP2:T5IP0, to set the interruptpriority. Note that while Timer2 or Timer4 controlsthe timer, the interrupt appears as a Timer3or Timer5 interrupt.6. Set the TON bit (= 1).The timer value at any point is stored in the registerpair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)always contains the most significant word of the count,while TMR2 (TMR4) contains the least significant word.To configure any of the timers for individual 16-bitoperation:1. Clear the T32 bit corresponding to that timer(T2CON for Timer2 and Timer3 orT4CON for Timer4 and Timer5).2. Select the timer prescaler ratio using theTCKPS1:TCKPS0 bits.3. Set the Clock and Gating modes using the TCSand TGATE bits.4. Load the timer period value into the PRx register.5. If interrupts are required, set the interrupt enablebit, TxIE; use the priority bits, TxIP2:TxIP0, toset the interrupt priority.6. Set the TON bit (TxCON = 1).© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 107

PIC24FJ128GA010 FAMILYFIGURE 11-1:TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAMT2CK(T4CK)GateSync1x01TONTCKPS1:TCKPS02Prescaler1, 8, 64, 256TCY00TGATETGATETCSSet T3IF (T5IF)10QQDCKPR3(PR5)PR2(PR4)ADC Event Trigger*EqualComparatorMSBLSBResetTMR3(TMR5)TMR2(TMR4)Sync16Read TMR2 (TMR4)Write TMR2 (TMR4)16TMR3HLD(TMR5HLD)16Data BusNote: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits arerespective to the T2CON and T4CON registers.* The ADC Event Trigger is available only on Timer4/5.DS39747E-page 108© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 11-2:TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAMT2CK(T4CK)GateSync1x01TONTCKPS1:TCKPS02Prescaler1, 8, 64, 256TGATE00Set T2IF (T4IF)10QQDCKTCYTCSTGATEResetTMR2 (TMR4)SyncEqualComparatorPR2 (PR4)FIGURE 11-3:TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAMT3CK(T5CK)Sync1x01TONTCKPS1:TCKPS02Prescaler1, 8, 64, 256TGATE00Set T3IF (T5IF)10QQDCKTCYTCSTGATEResetTMR3 (TMR5)ADC Event Trigger*EqualComparatorPR3 (PR5)* The ADC Event Trigger is available only on Timer4/5.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 109

PIC24FJ128GA010 FAMILYREGISTER 11-1:TxCON: TIMER2 AND TIMER4 CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON — TSIDL — — — — —bit 15 bit 8U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0— TGATE TCKPS1 TCKPS0 T32 (1) — TCS —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 TON: Timerx On bitWhen TxCON = 1:1 = Starts 32-bit Timerx/y0 = Stops 32-bit Timerx/yWhen TxCON = 0:1 = Starts 16-bit Timerx0 = Stops 16-bit Timerxbit 14 Unimplemented: Read as ‘0’bit 13 TSIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-7 Unimplemented: Read as ‘0’bit 6TGATE: Timerx Gated Time Accumulation Enable bitWhen TCS = 1:This bit is ignored.When TCS = 0:1 = Gated time accumulation enabled0 = Gated time accumulation disabledbit 5-4 TCKPS1:TCKPS0: Timer2 Input Clock Prescale Select bits11 = 1:25610 = 1:6401 = 1:800 = 1:1bit 3 T32: 32-Bit Timer Mode Select bit (1)1 = Timerx and Timery form a single 32-bit timer0 = Timerx and Timery act as two 16-bit timersbit 2 Unimplemented: Read as ‘0’bit 1TCS: Timerx Clock Source Select bit1 = External clock from pin TxCK (on the rising edge)0 = Internal clock (FOSC/2)bit 0 Unimplemented: Read as ‘0’Note 1:In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.DS39747E-page 110© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 11-2:TyCON: TIMER3 AND TIMER5 CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0TON (1) — TSIDL (1) — — — — —bit 15 bit 8U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0— TGATE (1) TCKPS1 (1) TCKPS0 (1) — — TCS (1) —bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 TON: Timery On bit (1)1 = Starts 16-bit Timery0 = Stops 16-bit Timerybit 14 Unimplemented: Read as ‘0’bit 13 TSIDL: Stop in Idle Mode bit (1)1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-7 Unimplemented: Read as ‘0’bit 6 TGATE: Timery Gated Time Accumulation Enable bit (1)When TCS = 1:This bit is ignored.When TCS = 0:1 = Gated time accumulation enabled0 = Gated time accumulation disabledbit 5-4 TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits (1)11 = 1:25610 = 1:6401 = 1:800 = 1:1bit 3-2 Unimplemented: Read as ‘0’bit 1 TCS: Timery Clock Source Select bit (1)1 = External clock from pin TyCK (on the rising edge)0 = Internal clock (FOSC/2)bit 0 Unimplemented: Read as ‘0’Note 1:When 32-bit operation is enabled (T2CON = 1), these bits have no effect on Timery operation; all timerfunctions are set through T2CON.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 111

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 112© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY12.0 INPUT CAPTURENote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 15. “Input Capture”(DS39701) in the “PIC24F FamilyReference Manual” for more information.The input capture module has multiple operatingmodes which are selected via the ICxCON register.The operating modes include:• Capture timer value on every falling edge of inputapplied at the ICx pin• Capture timer value on every rising edge of inputapplied at the ICx pin• Capture timer value on every fourth rising edge ofinput applied at the ICx pin• Capture timer value on every 16th rising edge ofinput applied at the ICx pin• Capture timer value on every rising and everyfalling edge of input applied at the ICx pin• Device wake-up from capture pin during CPUSleep and Idle modesThe input capture module has a four-level FIFO buffer.The number of capture events required to generate aCPU interrupt can be selected by the user.FIGURE 12-1:INPUT CAPTURE BLOCK DIAGRAMFrom 16-Bit TimersTMRyTMRx16 16ICx pinPrescalerCounter(1, 4, 16)3ICM (ICxCON)Mode SelectICxCONEdge Detection LogicandClock SynchronizerICOV, ICBNE (ICxCON)ICIInterruptLogicFIFOR/WLogic1 0ICxBUFICTMR(ICxCON)FIFOSystem BusSet Flag ICxIF(in IFSx Register)Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 113

PIC24FJ128GA010 FAMILY12.1 Input Capture RegistersREGISTER 12-1:ICxCON: INPUT CAPTURE x CONTROL REGISTERU-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — ICSIDL — — — — —bit 15 bit 8R/W-0 R/W-0 R/W-0 R-0, HC R/W-0, HC R/W-0 R/W-0 R/W-0ICTMR (1) ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0bit 7 bit 0Legend:HC = Hardware ClearableR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit1 = Input capture module will halt in CPU Idle mode0 = Input capture module will continue to operate in CPU Idle modebit 12-8 Unimplemented: Read as ‘0’bit 7 ICTMR: Input Capture x Timer Select bit (1)bit 6-5bit 4bit 3bit 2-01 = TMR2 contents are captured on capture event0 = TMR3 contents are captured on capture eventICI1:ICI0: Select Number of Captures per Interrupt bits11 = Interrupt on every fourth capture event10 = Interrupt on every third capture event01 = Interrupt on every second capture event00 = Interrupt on every capture eventICOV: Input Capture x Overflow Status Flag bit (read-only)1 = Input capture overflow occurred0 = No input capture overflow occurredICBNE: Input Capture x Buffer Empty Status bit (read-only)1 = Input capture buffer is not empty, at least one more capture value can be read0 = Input capture buffer is emptyICM2:ICM0: Input Capture x Mode Select bits111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edgedetect only, all other control bits are not applicable)110 = Unused (module disabled)101 = Capture mode, every 16th rising edge100 = Capture mode, every 4th rising edge011 = Capture mode, every rising edge010 = Capture mode, every falling edge001 = Capture mode, every edge (rising and falling) – ICI does not control interrupt generationfor this mode000 = Input capture module turned offNote 1:Timer selections may vary. Refer to the device data sheet for details.DS39747E-page 114© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY13.0 OUTPUT COMPARENote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 16. “OutputCompare” (DS39706) in the “PIC24FFamily Reference Manual” for moreinformation.FIGURE 13-1:OUTPUT COMPARE MODULE BLOCK DIAGRAMSet Flag bitOCxIF (1)OCxRS (1)OCxR (1)OutputLogicSRQOCx (1)3Output EnableComparatorOCM2:OCM0Mode SelectOCFA or OCFB (2)0 1OCTSEL 0 11616TMR register inputsfrom time bases(see Note 3).Period match signalsfrom time bases(see Note 3).Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5.2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5.3: Each output compare channel can use either Timer2 or Timer3.13.1 MODES OF OPERATIONEach output compare module has the following modesof operation:• Single Compare Match mode• Dual Compare Match mode generating:- Single Output Pulse mode- Continuous Output Pulse mode• Simple Pulse-Width Modulation mode:- with Fault protection input- without Fault protection input13.2 Setup for Single Output PulseGenerationWhen the OCM control bits (OCxCON) are set to‘100’, the selected output compare channel initializesthe OCx pin to the low state and generates a singleoutput pulse.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 115

PIC24FJ128GA010 FAMILYTo generate a single output pulse, the following stepsare required (these steps assume the timer source isinitially turned off, but this is not a requirement for themodule operation):1. Determine the instruction clock cycle time. Takeinto account the frequency of the external clockto the timer source (if one is used) and the timerprescaler settings.2. Calculate time to the rising edge of the outputpulse relative to the TMRy start value (0000h).3. Calculate the time to the falling edge of the pulsebased on the desired pulse width and the time tothe rising edge of the pulse.4. Write the values computed in steps 2 and 3above into the Compare register, OCxR, and theSecondary Compare register, OCxRS,respectively.5. Set the Timer Period register, PRy, to value equalto or greater than value in OCxRS, the SecondaryCompare register.6. Set the OCM bits to ‘100’ and the OCTSEL(OCxCON) bit to the desired timer source.The OCx pin state will now be driven low.7. Set the TON (TyCON) bit to ‘1’ whichenables the compare time base to count.8. Upon the first match between TMRy and OCxR,the OCx pin will be driven high.9. When the incrementing timer, TMRy, matches theSecondary Compare register, OCxRS, thesecond and trailing edge (high-to-low) of the pulseis driven onto the OCx pin. No additional pulsesare driven onto the OCx pin and it remains at low.As a result of the second compare match event,the OCxIF interrupt flag bit is set which will resultin an interrupt, if it is enabled, by setting theOCxIE bit. For further information on peripheralinterrupts, refer to Section 6.0 “InterruptController”.10. To initiate another single pulse output, change theTimer and Compare register settings, if needed,and then issue a write to set the OCM bits to ‘100’.Disabling and re-enabling of the timer and clearingthe TMRy register are not required, but maybe advantageous for defining a pulse from aknown event time boundary.The output compare module does not have to be disabledafter the falling edge of the output pulse. Anotherpulse can be initiated by rewriting the value of theOCxCON register.13.3 Setup for Continuous OutputPulse GenerationWhen the OCM control bits (OCxCON) are set to‘101’, the selected output compare channel initializesthe OCx pin to the low state and generates outputpulses on each and every compare match event.For the user to configure the module for the generationof a continuous stream of output pulses, the followingsteps are required (these steps assume the timersource is initially turned off, but this is not a requirementfor the module operation):1. Determine the instruction clock cycle time. Takeinto account the frequency of the external clockto the timer source (if one is used) and the timerprescaler settings.2. Calculate time to the rising edge of the outputpulse relative to the TMRy start value (0000h).3. Calculate the time to the falling edge of the pulse,based on the desired pulse width and the time tothe rising edge of the pulse.4. Write the values computed in step 2 and 3above into the Compare register, OCxR, andthe Secondary Compare register, OCxRS,respectively.5. Set Timer Period register, PRy, to value equal toor greater than value in OCxRS, the SecondaryCompare register.6. Set the OCM bits to ‘101’ and the OCTSEL bit tothe desired timer source. The OCx pin state willnow be driven low.7. Enable the compare time base by setting the TON(TyCON) bit to ‘1’.8. Upon the first match between TMRy and OCxR,the OCx pin will be driven high.9. When the compare time base, TMRy, matchesthe Secondary Compare register, OCxRS, thesecond and trailing edge (high-to-low) of the pulseis driven onto the OCx pin.10. As a result of the second compare match event,the OCxIF interrupt flag bit set.11. When the compare time base and the value in itsrespective Period register match, the TMRyregister resets to 0x0000 and resumes counting.12. Steps 8 through 11 are repeated and a continuousstream of pulses is generated, indefinitely. TheOCxIF flag is set on each OCxRS-TMRy comparematch event.DS39747E-page 116© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY13.4 Pulse-Width Modulation ModeThe following steps should be taken when configuringthe output compare module for PWM operation:1. Set the PWM period by writing to the selectedTimer Period register (PRy).2. Set the PWM duty cycle by writing to the OCxRSregister.3. Write the OCxR register with the initial dutycycle.4. Enable interrupts, if required, for the timer andoutput compare modules. The output compareinterrupt is required for PWM Fault pinutilization.5. Configure the output compare module for one oftwo PWM operation modes by writing to theOutput Compare mode bits OCM(OCxCON).6. Set the TMRy prescale value and enable thetime base by setting TON (TxCON) = 1.Note:The OCxR register should be initializedbefore the output compare module is firstenabled. The OCxR register becomes aRead-Only Duty Cycle register when themodule is operated in the PWM modes.The value held in OCxR will become thePWM duty cycle for the first PWM period.The contents of the Duty Cycle Bufferregister, OCxRS, will not be transferredinto OCxR until a time base period matchoccurs.13.4.1 PWM PERIODThe PWM period is specified by writing to PRy, theTimer Period register. The PWM period can becalculated using Equation 13-1.EQUATION 13-1:Note:CALCULATING THE PWMPERIOD (1)PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)where:PWM Frequency = 1/[PWM Period]Note 1:Based on TCY = TOSC * 2, Doze mode andPLL are disabled.A PRy value of N will produce a PWMperiod of N + 1 time base count cycles. Forexample, a value of 7 written into the PRyregister will yield a period consisting of8 time base cycles.13.4.2 PWM DUTY CYCLEThe PWM duty cycle is specified by writing to theOCxRS register. The OCxRS register can be written toat any time, but the duty cycle value is not latched intoOCxR until a match between PRy and TMRy occurs(i.e., the period is complete). This provides a doublebuffer for the PWM duty cycle and is essential for glitchlessPWM operation. In the PWM mode, OCxR is aread-only register.Some important boundary parameters of the PWM dutycycle include:• If the Duty Cycle register, OCxR, is loaded with0000h, the OCx pin will remain low (0% duty cycle).• If OCxR is greater than PRy (Timer Period register),the pin will remain high (100% duty cycle).• If OCxR is equal to PRy, the OCx pin will be lowfor one time base count value and high for allother count values.See Example 13-1 for PWM mode timing details.Table 13-1 shows example PWM frequencies andresolutions for a device operating at 10 MIPS.EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION (1)Maximum PWM Resolution (bits) =FCY( )log 10FPWM • (Timer Prescale Value)log 10 (2)bitsNote 1:Based on FCY = FOSC/2, Doze mode and PLL are disabled.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 117

PIC24FJ128GA010 FAMILYEXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS (1)1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz deviceclock rate) and a Timer2 prescaler setting of 1:1.TCY = 2/FOSC = 62.5 nsPWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μsPWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value)19.2 μs = (PR2 + 1) • 62.5 ns • 1PR2 = 3062. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:PWM Resolution = log 10 (FCY/FPWM)/log 10 2) bits= (log 10 (16 MHz/52.08 kHz)/log 10 2) bits= 8.3 bitsNote 1: Based on TCY = TOSC * 2, Doze mode and PLL are disabled.TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz) (1)PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHzTimer Prescaler Ratio 8 1 1 1 1 1 1Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001FhResolution (bits) 16 16 15 12 10 7 5Note 1: Based on TCY = TOSC * 2, Doze mode and PLL are disabled.TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHZ) (1)PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHzTimer Prescaler Ratio 8 1 1 1 1 1 1Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001FhResolution (bits) 16 16 15 12 10 7 5Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.DS39747E-page 118© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 13-1:OCxCON: OUTPUT COMPARE x CONTROL REGISTERU-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0— — OCSIDL — — — — —bit 15 bit 8U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0— — — OCFLT OCTSEL (1) OCM2 OCM1 OCM0bit 7 bit 0Legend:HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 OCSIDL: Stop Output Compare x Module Stop in Idle Control bit1 = Output capture x will halt in CPU Idle mode0 = Output capture x will continue to operate in CPU Idle modebit 12-5 Unimplemented: Read as ‘0’bit 4 OCFLT: PWM Fault Condition Status bit (1)1 = PWM Fault condition has occurred (cleared in HW only)0 = No PWM Fault condition has occurred (this bit is only used when OCM = 111)bit 3 OCTSEL: Output Compare x Timer Select bit (1)bit 2-01 = Timer3 is the clock source for output Compare x0 = Timer2 is the clock source for output Compare xOCM2:OCM0: Output Compare x Mode Select bits111 = PWM mode on OCx, Fault pin enabled (2)110 = PWM mode on OCx, Fault pin disabled (2)101 = Initialize OCx pin low, generate continuous output pulses on OCx pin100 = Initialize OCx pin low, generate single output pulse on OCx pin011 = Compare event toggles OCx pin010 = Initialize OCx pin high, compare event forces OCx pin low001 = Initialize OCx pin low, compare event forces OCx pin high000 = Output compare channel is disabledNote 1: Refer to the device data sheet for specific time bases available to the output compare module.2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 119

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 120© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY14.0 SERIAL PERIPHERALINTERFACE (SPI)Note:The Serial Peripheral Interface (SPI) module is a synchronousserial interface useful for communicating withother peripheral or microcontroller devices. Theseperipheral devices may be serial EEPROMs, shift registers,display drivers, A/D Converters, etc. The SPImodule is compatible with Motorola’s SPI and SIOPinterfaces.The module supports operation in two buffer modes. InStandard mode, data is shifted through a single serialbuffer. In Enhanced Buffer mode, data is shiftedthrough an 8-level FIFO buffer.Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 23. “SerialPeripheral Interface (SPI)” (DS39699) inthe PIC24F Family Reference Manual formore information.Do not perform read-modify-write operations(such as bit-oriented instructions) onthe SPIxBUF register, in either Standardor Enhanced Buffer mode.The module also supports a basic framed SPI protocolwhile operating in either Master or Slave modes. A totalof four framed SPI configurations are supported.The SPI serial interface consists of four pins:• SDIx: Serial Data Input• SDOx: Serial Data Output• SCKx: Shift Clock Input or Output• SSx: Active-Low Slave Select or FrameSynchronization I/O PulseThe SPI module can be configured to operate, using 2,3 or 4 pins. In the 3-pin mode, SSx is not used. In the2-pin mode, both SDOx and SSx are not used.A block diagram of the module is shown in Figure 14-1and Figure 14-2.To set up the SPI module for the Standard Master modeof operation:1. If using interrupts:a) Clear the SPIxIF bit in the respective IFSxregister.b) Set the SPIxIE bit in the respective IECxregister.c) Write the SPIxIP bits in the respective IPCxregister to set the interrupt priority.2. Write the desired settings to the SPIxCONregister with MSTEN (SPIxCON1) = 1.3. Clear the SPIROV bit (SPIxSTAT).4. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).5. Write the data to be transmitted to the SPIxBUFregister. Transmission (and reception) will startas soon as data is written to the SPIxBUFregister.To set up the SPI module for the Standard Slave modeof operation:1. Clear the SPIxBUF register.2. If using interrupts:a) Clear the SPIxIF bit in the respective IFSxregister.b) Set the SPIxIE bit in the respective IECxregister.c) Write the SPIxIP bits in the respective IPCxregister to set the interrupt priority.3. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1) = 0.4. Clear the SMP bit.5. If the CKE bit is set, then the SSEN bit(SPIxCON1) must be set to enable the SSxpin.6. Clear the SPIROV bit (SPIxSTAT).7. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).Note:In this section, the SPI modules arereferred to together as SPIx or separatelyas SPI1 and SPI2. Special Function Registerswill follow a similar notation. Forexample, SPIxCON refers to the controlregister for the SPI1 or SPI2 module.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 121

PIC24FJ128GA010 FAMILYTo set up the SPI module for the Enhanced BufferMaster mode of operation:1. If using interrupts:a) Clear the SPIxIF bit in the respective IFSxregister.b) Set the SPIxIE bit in the respective IECxregister.c) Write the SPIxIP bits in the respective IPCxregister.2. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1) = 1.3. Clear the SPIROV bit (SPIxSTAT).4. Select Enhanced Buffer mode by setting theSPIBEN bit (SPIxCON2).5. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).6. Write the data to be transmitted to the SPIxBUFregister. Transmission (and reception) will startas soon as data is written to the SPIxBUFregister.To set up the SPI module for the Enhanced BufferSlave mode of operation:1. Clear the SPIxBUF register.2. If using interrupts:• Clear the SPIxIF bit in the respective IFSxregister.• Set the SPIxIE bit in the respective IECxregister.• Write the SPIxIP bits in the respective IPCxregister to set the interrupt priority.3. Write the desired settings to the SPIxCON1 andSPIxCON2 registers with MSTEN(SPIxCON1) = 0.4. Clear the SMP bit.5. If the CKE bit is set, then the SSEN bit must beset, thus enabling the SSx pin.6. Clear the SPIROV bit (SPIxSTAT).7. Select Enhanced Buffer mode by setting theSPIBEN bit (SPIxCON2).8. Enable SPI operation by setting the SPIEN bit(SPIxSTAT).FIGURE 14-1:SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)SCKx1:1 to 1:8SecondaryPrescaler1:1/4/16/64PrimaryPrescalerFCYSSx/FSYNCxSyncControlControlClockSelectEdgeSPIxCON1SDOxShift ControlSPIxCON1SDIxbit 0SPIxSREnableMaster ClockTransferTransferSPIxBUFRead SPIxBUFWrite SPIxBUF16Internal Data BusDS39747E-page 122© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 14-2:SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)SCKxSSx/FSYNCxSyncControlControlClockSelectEdge1:1 to 1:8SecondaryPrescaler1:1/4/16/64PrimaryPrescalerFCYSPIxCON1SDOxShift ControlSPIxCON1SDIxbit0SPIxSREnableMaster ClockTransferTransfer8-Level FIFOReceive Buffer8-Level FIFOTransmit BufferSPIxBUFRead SPIxBUFWrite SPIxBUF16Internal Data Bus© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 123

PIC24FJ128GA010 FAMILYREGISTER 14-1:SPIxSTAT: SPIx STATUS AND CONTROL REGISTERR/W-0 U-0 R/W-0 U-0 U-0 R-0 R-0 R-0SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0bit 15 bit 8R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIREFbit 7 bit 0Legend:C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 SPIEN: SPIx Enable bit1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins0 = Disables modulebit 14 Unimplemented: Read as ‘0’bit 13 SPISIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-11 Unimplemented: Read as ‘0’bit 10-8bit 7bit 6bit 5bit 4-2SPIBEC2:SPIBEC0: SPIx Buffer Element Count bitsMaster mode:Number of SPI transfers pending.Slave mode:Number of SPI transfers unread.SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)1 = SPIx Shift register is empty and ready to send or receive0 = SPIx Shift register is not emptyRead as ‘0’SPIROV: Receive Overflow Flag bit1 = A new byte/word is completely received and discarded. The user software has not read the previousdata in the SPIxBUF register.0 = No overflow has occurredSRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)1 = Receive FIFO is empty0 = Receive FIFO is not empty’SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set)110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set)010 = Interrupt when SPIx receive buffer is 3/4 or more full001 = Interrupt when data is available in receive buffer (SRMPT bit is set)000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty(SRXMPT bit set)DS39747E-page 124© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 14-1:SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)bit 1bit 0SPITBF: SPIx Transmit Buffer Full Status bit1 = Transmit not yet started, SPIxTXB is full0 = Transmit started, SPIxTXB is emptyIn Standard Buffer mode:Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automaticallycleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.In Enhanced Buffer mode:Automatically set in hardware when CPU writes SPIxBUF location, loading the last available bufferlocation. Automatically cleared in hardware when a buffer location is available for a CPU write.SPIRBF: SPIx Receive Buffer Full Status bit1 = Receive complete, SPIxRXB is full0 = Receive is not complete, SPIxRXB is emptyIn Standard Buffer mode:Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automaticallycleared in hardware when core reads SPIxBUF location, reading SPIxRXB.In Enhanced Buffer mode:Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unreadbuffer location. Automatically cleared in hardware when a buffer location is available for a transfer fromSPIxSR.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 125

PIC24FJ128GA010 FAMILYREGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0— — — DISSCK DISSDO MODE16 SMP CKE (1)bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-13 Unimplemented: Read as ‘0’bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)1 = Internal SPI clock is disabled, pin functions as I/O0 = Internal SPI clock is enabledbit 11 DISSDO: Disable SDOx pin bit1 = SDOx pin is not used by module; pin functions as I/O0 = SDOx pin is controlled by the modulebit 10 MODE16: Word/Byte Communication Select bit1 = Communication is word-wide (16 bits)0 = Communication is byte-wide (8 bits)bit 9SMP: SPIx Data Input Sample Phase bitMaster mode:1 = Input data sampled at end of data output time0 = Input data sampled at middle of data output timeSlave mode:SMP must be cleared when SPIx is used in Slave mode.bit 8 CKE: SPIx Clock Edge Select bit (1)1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)bit 7SSEN: Slave Select Enable (Slave mode) bit1 = SSx pin used for Slave mode0 = SSx pin not used by module. Pin controlled by port function.bit 6bit 5bit 4-2bit 1-0CKP: Clock Polarity Select bit1 = Idle state for clock is a high level; active state is a low level0 = Idle state for clock is a low level; active state is a high levelMSTEN: Master Mode Enable bit1 = Master mode0 = Slave modeSPRE2:SPRE0: Secondary Prescale (Master mode) bits111 = Secondary prescale 1:1110 = Secondary prescale 2:1...000 = Secondary prescale 8:1PPRE1:PPRE0: Primary Prescale (Master mode) bits11 = Primary prescale 1:110 = Primary prescale 4:101 = Primary prescale 16:100 = Primary prescale 64:1Note 1:The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPImodes (FRMEN = 1).DS39747E-page 126© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0FRMEN SPIFSD SPIFPOL — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — SPIFE SPIBENbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 FRMEN: Framed SPIx Support bit1 = Framed SPIx support enabled0 = Framed SPIx support disabledbit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit1 = Frame sync pulse input (slave)0 = Frame sync pulse output (master)bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)1 = Frame sync pulse is active-high0 = Frame sync pulse is active-lowbit 12-2 Unimplemented: Read as ‘0’bit 1SPIFE: Frame Sync Pulse Edge Select bit1 = Frame sync pulse coincides with first bit clock0 = Frame sync pulse precedes first bit clockbit 0SPIBEN: Enhanced Buffer Enable bit1 = Enhanced Buffer enabled0 = Enhanced Buffer disabled (Legacy mode)© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 127

PIC24FJ128GA010 FAMILYFIGURE 14-3:SPI MASTER/SLAVE CONNECTION (STANDARD MODE)PROCESSOR 1 (SPI Master)PROCESSOR 2 (SPI Slave)SDOxSDIxSerial Receive Buffer(SPIxRXB)Serial Receive Buffer(SPIxRXB)Shift Register(SPIxSR)MSbLSbSDIxSDOxMSbShift Register(SPIxSR)LSbSerial Transmit Buffer(SPIxTXB)Serial Transmit Buffer(SPIxTXB)SPIx Buffer(SPIxBUF)SCKxSerial ClockSCKxSPIx Buffer(SPIxBUF)SSx(MSTEN (SPIxCON1 = 1))(SSEN (SPIxCON1) = 1 and MSTEN (SPIxCON1) = 0)Note 1: Using the SSx pin in the Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memorymapped to SPIxBUF.FIGURE 14-4:SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)PROCESSOR 1 (SPI Enhanced Buffer Master)SDOxPROCESSOR 2 (SPI Enhanced Buffer Slave)SDIxShift Register(SPIxSR)SDIxSDOxShift Register(SPIxSR)MSbLSbMSbLSb8-Level FIFO Buffer8-Level FIFO BufferSPIx Buffer(SPIxBUF)SCKxSerial ClockSCKxSPIx Buffer(SPIxBUF)SSxSSxMSTEN (SPIxCON1 = 1 andSPIBEN (SPIxCON2) = 1SSEN (SPIxCON1) = 1 andMSTEN (SPIxCON1) = 0 andSPIBEN (SPIxCON2) = 1Note 1: Using the SSx pin in Slave mode of operation is optional.2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memorymapped to SPIxBUF.DS39747E-page 128© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 14-5:SPI MASTER, FRAME MASTER CONNECTION DIAGRAMPIC24F(SPI Slave, Frame Slave)PROCESSOR 2SDOxSDIxSDIxSCKxSSxSerial ClockFrame SyncPulseSDOxSCKxSSxFIGURE 14-6:SPI MASTER, FRAME SLAVE CONNECTION DIAGRAMPIC24FSPI Master, Frame Slave)PROCESSOR 2SDOxSDIxSDIxSCKxSSxSerial ClockFrame SyncPulseSDOxSCKxSSxFIGURE 14-7:SPI SLAVE, FRAME MASTER CONNECTION DIAGRAMPIC24F(SPI Slave, Frame Slave)PROCESSOR 2SDOxSDIxSDIxSCKxSSxSerial ClockFrame Sync.PulseSDOxSCKxSSxFIGURE 14-8:SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAMPIC24F(SPI Master, Frame Slave)PROCESSOR 2SDOxSDIxSDIxSCKxSSxSerial ClockFrame SyncPulseSDOxSCKxSSx© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 129

PIC24FJ128GA010 FAMILYEQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED (1)FSCK =FCYPrimary Prescaler * Secondary PrescalerNote 1:Based on FCY = FOSC/2, Doze mode and PLL are disabled.TABLE 14-1: SAMPLE SCK FREQUENCIES (1,2)FCY = 16 MHzSecondary Prescaler Settings1:1 2:1 4:1 6:1 8:1Primary Prescaler Settings 1:1 Invalid 8000 4000 2667 20004:1 4000 2000 1000 667 50016:1 1000 500 250 167 12564:1 250 125 63 42 31FCY = 5 MHzPrimary Prescaler Settings 1:1 5000 2500 1250 833 6254:1 1250 625 313 208 15616:1 313 156 78 52 3964:1 78 39 20 13 10Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled.2: SCKx frequencies shown in kHz.DS39747E-page 130© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY15.0 INTER-INTEGRATED CIRCUIT(I 2 C)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 24. “Inter-Integrated Circuit (I 2 C)” (DS39702)in the “PIC24F Family Reference Manual”for more information.The Inter-Integrated Circuit (I 2 C) module is a serialinterface useful for communicating with other peripheralor microcontroller devices. These peripheraldevices may be serial EEPROMs, display drivers, A/DConverters, etc.The I 2 C module supports these features:• Independent master and slave logic• 7-bit and 10-bit device addresses• General call address, as defined in the I 2 C protocol• Clock stretching to provide delays for theprocessor to respond to a slave data request• Both 100 kHz and 400 kHz bus specifications.• Configurable address masking• Multi-Master modes to prevent loss of messagesin arbitration• Bus Repeater mode, allowing the acceptance ofall messages as a slave regardless of the address• Automatic SCLA block diagram of the module is shown in Figure 15-1.15.1 Communicating as a Master in aSingle Master EnvironmentThe details of sending a message in Master modedepends on the communications protocol for the devicebeing communicated with. Typically, the sequence ofevents is as follows:1. Assert a Start condition on SDAx and SCLx.2. Send the I 2 C device address byte to the slavewith a write indication.3. Wait for and verify an Acknowledge from theslave.4. Send the first data byte (sometimes known asthe command) to the slave.5. Wait for and verify an Acknowledge from theslave.6. Send the serial memory address low byte to theslave.7. Repeat steps 4 and 5 until all data bytes aresent.8. Assert a Repeated Start condition on SDAx andSCLx.9. Send the device address byte to the slave witha read indication.10. Wait for and verify an Acknowledge from theslave.11. Enable master reception to receive serialmemory data.12. Generate an ACK or NACK condition at the endof a received byte of data.13. Generate a Stop condition on SDAx and SCLx.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 131

PIC24FJ128GA010 FAMILYFIGURE 15-1:I 2 C BLOCK DIAGRAMInternalData BusI2CxRCVReadSCLxShiftClockI2CxRSRLSBSDAxMatch DetectAddress MatchWriteI2CxMSKWriteReadI2CxADDReadStart and StopBit DetectWriteStart and StopBit GenerationI2CxSTATCollisionDetectAcknowledgeGenerationControl LogicI2CxCONReadWriteReadClockStretchingWriteI2CxTRNShift ClockLSBReadReloadControlWriteBRG Down CounterI2CxBRGTCY/2ReadDS39747E-page 132© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY15.3 Slave Address Masking15.2 Setting Baud Rate WhenEQUATION 15-1: (1)Operating as a Bus MasterTo compute the Baud Rate Generator reload value, usethe following equation:I2CxBRG = (FCY/FSCL – FCY/10,000,000) – 1Note 1:Based on FCY = FOSC/2; Doze mode andPLL are disabled.The I2CxMSK register (Register 15-3) designatesaddress bit positions as “don’t care” for both 7-Bit and10-Bit Addressing modes. Setting a particular bit location(= 1) in the I2CxMSK register causes the slavemodule to respond, whether the correspondingaddress bit value is a ‘0’ or ‘1’. For example, whenI2CxMSK is set to ‘00100000’, the slave module willdetect both addresses ‘0000000’ and ‘00100000’.To enable address masking, the IPMI (IntelligentPeripheral Management Interface) must be disabled byclearing the IPMIEN bit (I2CxCON).TABLE 15-1: I 2 C CLOCK RATES (1,3,4)RequiredSystemFSCLFCY(Decimal)I2CxBRG Value(Hexadecimal)ActualFSCL100 kHz 16 MHz 157 9D 100 kHz100 kHz 8 MHz 78 4E 100 kHz100 kHz 4 MHz 39 27 99 kHz400 kHz 16 MHz 37 25 404 kHz400 kHz 8 MHz 18 12 404 kHz400 kHz 4 MHz 9 9 385 kHz (2)400 kHz 2 MHz 4 4 385 kHz (2)1 MHz 16 MHz 13 D 1,026 KHz1MHz 8MHz 6 6 1,026KHz1MHz 4MHz 3 3 909 KHzLegend: Shaded rows represent invalid reload values for a given FSCL and FCY.Note 1: Based on TCY = TOSC * 2 (2) , Doze mode and PLL are disabled.2: This is the closest value to 400 kHz for this value of FCY.3: FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.4: I2CxBRG cannot have a value of less than 2.As a result of changes in the I2C protocol, several I2Caddresses are reserved and will not be acknowledgedin Slave mode.TABLE 15-2: RESERVED I 2 C ADDRESSES (1)Address masking does not affect behavior. Refer toTable 15-2 for a summary of these reserved addresses.Slave Address R/W Bit Description0000 000 0 General Call Address (2)0000 000 1 Start Byte0000 001 x CBUS Address0000 010 x Reserved0000 011 x Reserved0000 1xx x HS Mode Master Code1111 1xx x Reserved1111 0xx x 10-Bit Slave Upper Byte (3)Note 1: The above address bits will not cause an address match, independent of address mask settings.2: Address will be Acknowledged only if GCEN = 1.3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 133

PIC24FJ128GA010 FAMILYREGISTER 15-1:I2CxCON: I2Cx CONTROL REGISTERR/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMENbit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HCGCEN STREN ACKDT ACKEN RCEN PEN RSEN SENbit 7 bit 0Legend:HC = Hardware ClearableR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 I2CEN: I2Cx Enable bit1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins0 = Disables I2Cx module. All I 2 C pins are controlled by port functions.bit 14 Unimplemented: Read as ‘0’bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6I2CSIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters an Idle mode0 = Continue module operation in Idle modeSCLREL: SCLx Release Control bit (when operating as I 2 C slave)1 = Release SCLx clock0 = Hold SCLx clock low (clock stretch)If STREN = 1:Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clearat beginning of slave transmission. Hardware clear at end of slave reception.If STREN = 0:Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slavetransmission.IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit1 = IPMI Support mode is enabled; all addresses Acknowledged0 = IPMI mode disabledA10M: 10-Bit Slave Address bit1 = I2CxADD is a 10-bit slave address0 = I2CxADD is a 7-bit slave addressDISSLW: Disable Slew Rate Control bit1 = Slew rate control disabled0 = Slew rate control enabledSMEN: SMBus Input Levels bit1 = Enable I/O pin thresholds compliant with SMBus specification0 = Disable SMBus input thresholdsGCEN: General Call Enable bit (when operating as I 2 C slave)1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled forreception)0 = General call address disabledSTREN: SCLx Clock Stretch Enable bit (when operating as I 2 C slave)Used in conjunction with SCLREL bit.1 = Enable software or receive clock stretching0 = Disable software or receive clock stretchingDS39747E-page 134© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 15-1:I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)bit 5bit 4bit 3bit 2bit 1bit 0ACKDT: Acknowledge Data bit (When operating as I 2 C master. Applicable during master receive.)Value that will be transmitted when the software initiates an Acknowledge sequence.1 = Send NACK during Acknowledge0 = Send ACK during AcknowledgeACKEN: Acknowledge Sequence Enable bit(When operating as I 2 C master. Applicable during master receive.)1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardwareclear at end of master Acknowledge sequence.0 = Acknowledge sequence not in progressRCEN: Receive Enable bit (when operating as I 2 C master)1 = Enables Receive mode for I 2 C. Hardware clear at end of eighth bit of master receive data byte.0 = Receive sequence not in progressPEN: Stop Condition Enable bit (when operating as I 2 C master)1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.0 = Stop condition not in progressRSEN: Repeated Start Condition Enabled bit (when operating as I 2 C master)1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of masterRepeated Start sequence.0 = Repeated Start condition not in progressSEN: Start Condition Enabled bit (when operating as I 2 C master)1 = Initiate Start condition on SDA and SCL pins. Hardware clear at end of master Start sequence.0 = Start condition not in progress© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 135

PIC24FJ128GA010 FAMILYREGISTER 15-2:I2CxSTAT: I2Cx STATUS REGISTERR-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSCACKSTAT TRSTAT — — — BCL GCSTAT ADD10bit 15 bit 8R/C-0, HSC R/C-0, HSC R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSCIWCOL I2COV D/A P S R/W RBF TBFbit 7 bit 0Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15ACKSTAT: Acknowledge Status bit1 = NACK received from slave0 = ACK received from slaveHardware set or clear at end of slave Acknowledge.bit 14 TRSTAT: Transmit Status bit (When operating as I 2 C master. Applicable to master transmit operation.)1 = Master transmit is in progress (8 bits + ACK)0 = Master transmit is not in progressHardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.bit 13-11 Unimplemented: Read as ‘0’bit 10bit 9bit 8bit 7bit 6bit 5bit 4BCL: Master Bus Collision Detect bit1 = A bus collision has been detected during a master operation0 = No collisionHardware set at detection of bus collision.GCSTAT: General Call Status bit1 = General call address was received0 = General call address was not receivedHardware set when address matches general call address. Hardware clear at Stop detection.ADD10: 10-Bit Address Status bit1 = 10-bit address was matched0 = 10-bit address was not matchedHardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.IWCOL: Write Collision Detect bit1 = An attempt to write the I2CxTRN register failed because the I 2 C module is busy0 = No collisionHardware set at occurrence of write to I2CxTRN while busy (cleared by software).I2COV: Receive Overflow Flag bit1 = A byte was received while the I2CxRCV register is still holding the previous byte0 = No overflowHardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).D/A: Data/Address bit (when operating as I 2 C slave)1 = Indicates that the last byte received was data0 = Indicates that the last byte received was device addressHardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte.P: Stop bit1 = Indicates that a Stop bit has been detected last0 = Stop bit was not detected lastHardware set or clear when Start, Repeated Start or Stop detected.DS39747E-page 136© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 15-2:I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)bit 3bit 2bit 1bit 0S: Start bit1 = Indicates that a Start (or Repeated Start) bit has been detected last0 = Start bit was not detected lastHardware set or clear when Start, Repeated Start or Stop detected.R/W: Read/Write bit Information (when operating as I 2 C slave)1 = Read – indicates data transfer is output from slave0 = Write – indicates data transfer is input to slaveHardware set or clear after reception of I 2 C device address byte.RBF: Receive Buffer Full Status bit1 = Receive complete, I2CxRCV is full0 = Receive not complete, I2CxRCV is emptyHardware set when I2CxRCV written with received byte. Hardware clear when software reads I2CxRCV.TBF: Transmit Buffer Full Status bit1 = Transmit in progress, I2CxTRN is full0 = Transmit complete, I2CxTRN is emptyHardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 137

PIC24FJ128GA010 FAMILYREGISTER 15-3:I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTERU-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — AMSK9 AMSK8bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-10 Unimplemented: Read as ‘0’bit 9-0 AMSK9:AMSK0: Mask for Address Bit x Select bits1 = Enable masking for bit x of incoming message address; bit match not required in this position0 = Disable masking for bit x; bit match required in this positionDS39747E-page 138© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY16.0 UNIVERSAL ASYNCHRONOUSRECEIVER TRANSMITTER(UART)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 21. “UART”(DS39708) in the “PIC24F FamilyReference Manual” for more information.The Universal Asynchronous Receiver Transmitter(UART) module is one of the serial I/O modulesavailable in the PIC24F device <strong>family</strong>. The UART is afull-duplex asynchronous system that can communicatewith peripheral devices, such as personal computers,LIN, RS-232 and RS-485 interfaces. The modulealso supports a hardware flow control option with theUxCTS and UxRTS pins and also includes an IrDAencoder and decoder.The primary features of the UART module are:• Full-Duplex, 8 or 9-Bit Data Transmission throughthe UxTX and UxRX pins• Even, Odd or No Parity Options (for 8-bit data)• One or Two Stop bits• Hardware Flow Control Option with UxCTS andUxRTS pins• Fully Integrated Baud Rate Generator with 16-BitPrescaler• Baud Rates Ranging from 1 Mbps to 15 bps at16 MIPS• 4-Deep First-In-First-Out (FIFO) Transmit DataBuffer• 4-Deep, FIFO Receive Data Buffer• Parity, Framing and Buffer Overrun Error Detection• Support for 9-bit mode with Address Detect(9th bit = 1)• Transmit and Receive Interrupts• Loopback mode for Diagnostic Support• Support for Sync and Break Characters• Supports Automatic Baud Rate Detection• IrDA Encoder and Decoder Logic• 16x Baud Clock Output for IrDA SupportA simplified block diagram of the UART is shown inFigure 16-1. The UART module consists of these keyimportant hardware elements:• Baud Rate Generator• Asynchronous Transmitter• Asynchronous ReceiverFIGURE 16-1:UART SIMPLIFIED BLOCK DIAGRAMBaud Rate GeneratorIrDA ®BCLKxHardware Flow ControlUARTx ReceiverUxRTSUxCTSUxRXUARTx TransmitterUxTX© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 139

PIC24FJ128GA010 FAMILY16.1 UART Baud Rate Generator (BRG)The UART module includes a dedicated 16-bit BaudRate Generator. The BRGx register controls the periodof a free-running, 16-bit timer. Equation 16-1 shows theformula for computation of the baud rate withBRGH = 0.EQUATION 16-1:Note 1:Baud Rate =UART BAUD RATE WITHBRGH = 0 (1)FCY16 • (BRGx + 1)FCYBRGx = – 116 • Baud RateBased on FCY = FOSC/2; Doze modeand PLL are disabled.Example 16-1 shows the calculation of the baud rateerror for the following conditions:• FCY = 4 MHz• Desired Baud Rate = 9600The maximum baud rate (BRGH = 0) possible isFCY/16 (for BRGx = 0), and the minimum baud ratepossible is FCY/(16 * 65536).Equation 16-2 shows the formula for computation ofthe baud rate with BRGH = 1.EQUATION 16-2:Note 1:Baud Rate =UART BAUD RATE WITHBRGH = 1 (1)FCY4 • (BRGx + 1)FCYBRGx = – 14 • Baud RateBased on FCY = FOSC/2; Doze modeand PLL are disabled.The maximum baud rate (BRGH = 1) possible is FCY/4(for BRGx = 0) and the minimum baud rate possible isFCY/(4 * 65536).Writing a new value to the BRGx register causes theBRG timer to be reset (cleared). This ensures the BRGdoes not wait for a timer overflow before generating thenew baud rate.EXAMPLE 16-1: BAUD RATE ERROR CALCULATION (BRGH = 0) (1)Desired Baud Rate = FCY/(16 (BRGx + 1))Solving for BRGx value:BRGx = ((FCY/Desired Baud Rate)/16) – 1BRGx = ((4000000/9600)/16) – 1BRGx = 25Calculated Baud Rate = 4000000/(16 (25 + 1))= 9615Error = (Calculated Baud Rate – Desired Baud Rate)Desired Baud Rate= (9615 – 9600)/9600= 0.16%Note 1:Based on FCY = FOSC/2; Doze mode and PLL are disabled.DS39747E-page 140© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY16.2 Transmitting in 8-Bit Data Mode1. Set up the UART:a) Write appropriate values for data, parity andStop bits.b) Write appropriate baud rate value to theBRGx register.c) Set up transmit and receive interrupt enableand priority bits.2. Enable the UART.3. Set the UTXEN bit (causes a transmit interrupt).4. Write data byte to lower byte of TXxREG word.The value will be immediately transferred to theTransmit Shift Register (TSR), and the serial bitstream will start shifting out with next rising edgeof the baud clock.5. Alternately, the data byte may be transferredwhile UTXEN = 0, and then the user may setUTXEN. This will cause the serial bit stream tobegin immediately because the baud clock willstart from a cleared state.6. A transmit interrupt will be generated as perinterrupt control bit, UTXISELx.16.3 Transmitting in 9-Bit Data Mode1. Set up the UART (as described in Section 16.2“Transmitting in 8-Bit Data Mode”).2. Enable the UART.3. Set the UTXEN bit (causes a transmit interrupt).4. Write UxTXREG as a 16-bit value only.5. A word write to UxTXREG triggers the transferof the 9-bit data to the TSR. Serial bit stream willstart shifting out with the first rising edge of thebaud clock.6. A transmit interrupt will be generated as per thesetting of control bit, UTXISELx.16.4 Break and Sync TransmitSequenceThe following sequence will send a message frameheader made up of a Break, followed by an auto-baudSync byte.1. Configure the UART for the desired mode.2. Set UTXEN and UTXBRK – sets up the Breakcharacter,3. Load the UxTXREG with a dummy character toinitiate transmission (value is ignored).4. Write ‘55h’ to UxTXREG – loads Sync characterinto the transmit FIFO.5. After the Break has been sent, the UTXBRK bitis reset by hardware. The Sync character nowtransmits.16.5 Receiving in 8-Bit or 9-Bit DataMode1. Set up the UART (as described in Section 16.2“Transmitting in 8-Bit Data Mode”).2. Enable the UART.3. A receive interrupt will be generated when oneor more data characters have been received asper interrupt control bit, URXISELx.4. Read the OERR bit to determine if an overrunerror has occurred. The OERR bit must be resetin software.5. Read UxRXREG.The act of reading the UxRXREG character will movethe next character to the top of the receive FIFO,including a new set of PERR and FERR values.16.6 Operation of UxCTS and UxRTSControl PinsUARTx Clear to Send (UxCTS) and Request to Send(UxRTS) are the two hardware controlled pins that areassociated with the UART module. These two pinsallow the UART to operate in Simplex and Flow Controlmode. They are implemented to control the transmissionand reception between the Data TerminalEquipment (DTE). The UEN bits in the UxMODEregister configure these pins.16.7 Infrared SupportThe UART module provides two types of infrared UARTsupport: one is the IrDA clock output to support externalIrDA encoder and decoder device (legacy modulesupport) and the other is the full implementation of theIrDA encoder and decoder.16.8 External IrDA Support – IrDAClock OutputTo support external IrDA encoder and decoder devices,the BCLKx pin (same as the UxRTS pin) can beconfigured to generate the 16x baud clock. WithUEN = 11, the BCLKx pin will output the 16xbaud clock if the UART module is enabled. It can beused to support the IrDA codec chip.16.9 Built-in IrDA Encoder and DecoderThe UART has full implementation of the IrDA encoderand decoder as part of the UART module. The built-inIrDA encoder and decoder functionality is enabledusing the IREN bit UxMODE. When enabled(IREN = 1), the receive pin (UxRX) acts as the inputfrom the infrared receiver. The transmit pin (UxTX) actsas the output to the infrared transmitter.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 141

PIC24FJ128GA010 FAMILYREGISTER 16-1:UxMODE: UARTx MODE REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0UARTEN — USIDL IREN (1) RTSMD — UEN1 UEN0bit 15 bit 8R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSELbit 7 bit 0Legend:HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 UARTEN: UARTx Enable bit1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimalbit 14 Unimplemented: Read as ‘0’bit 13 USIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12 IREN: IrDA Encoder and Decoder Enable bit (1)1 = IrDA encoder and decoder enabled0 = IrDA encoder and decoder disabledbit 11 RTSMD: Mode Selection for UxRTS Pin bit1 = UxRTS pin in Simplex mode0 = UxRTS pin in Flow Control modebit 10 Unimplemented: Read as ‘0’bit 9-8bit 7bit 6bit 5bit 4bit 3UEN1:UEN0: UARTx Enable bits11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latchesWAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared inhardware on following rising edge0 = No wake-up enabledLPBACK: UARTx Loopback Mode Select bit1 = Enable Loopback mode0 = Loopback mode is disabledABAUD: Auto-Baud Enable bit1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h);cleared in hardware upon completion0 = Baud rate measurement disabled or completedRXINV: Receive Polarity Inversion bit1 = UxRX Idle state is ‘0’0 = UxRX Idle state is ‘1’BRGH: High Baud Rate Enable bit1 = BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)0 = BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).DS39747E-page 142© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 16-1:UxMODE: UARTx MODE REGISTER (CONTINUED)bit 2-1bit 0PDSEL1:PDSEL0: Parity and Data Selection bits11 = 9-bit data, no parity10 = 8-bit data, odd parity01 = 8-bit data, even parity00 = 8-bit data, no paritySTSEL: Stop Bit Selection bit1 = Two Stop bits0 = One Stop bitNote 1: This feature is only available for the 16x BRG mode (BRGH = 0).© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 143

PIC24FJ128GA010 FAMILYREGISTER 16-2:UxSTA: UARTx STATUS AND CONTROL REGISTERR/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1UTXISEL1 TXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMTbit 15 bit 8R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDAbit 7 bit 0Legend: C = Clearable bit HC = Hardware Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15,13UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits11 = Reserved; do not use10 = Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmitbuffer becomes empty01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operationsare completed00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at leastone character open in the transmit buffer)bit 14 TXINV: Transmit Polarity Inversion bitIREN = 0:1 = TX Idle state is ‘0’0 = TX Idle state is ‘1’IREN = 1:1 = IrDA encoded TX Idle state is ‘1’0 = IrDA encoded TX Idle state is ‘0’bit 12 Unimplemented: Read as ‘0’bit 11bit 10bit 9bit 8UTXBRK: Transmit Break bit1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;cleared by hardware upon completion0 = Sync Break transmission disabled or completedUTXEN: Transmit Enable bit1 = Transmit enabled, UxTX pin controlled by UARTx0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT.UTXBF: Transmit Buffer Full Status bit (read-only)1 = Transmit buffer is full0 = Transmit buffer is not full, at least one more character can be writtenTRMT: Transmit Shift Register Empty bit (read-only)1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)0 = Transmit Shift Register is not empty, a transmission is in progress or queuedbit 7-6 URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer;receive buffer has one or more charactersbit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.0 = Address Detect mode disabledDS39747E-page 144© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 16-2:UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)bit 4bit 3bit 2bit 1bit 0RIDLE: Receiver Idle bit (read-only)1 = Receiver is Idle0 = Receiver is activePERR: Parity Error Status bit (read-only)1 = Parity error has been detected for the current character (character at the top of the receive FIFO)0 = Parity error has not been detectedFERR: Framing Error Status bit (read-only)1 = Framing error has been detected for the current character (character at the top of the receive FIFO)0 = Framing error has not been detectedOERR: Receive Buffer Overrun Error Status bit (clear/read-only)1 = Receive buffer has overflowed0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will resetthe receiver buffer and the RSR to the empty state)URXDA: Receive Buffer Data Available bit (read-only)1 = Receive buffer has data, at least one more character can be read0 = Receive buffer is empty© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 145

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 146© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY17.0 PARALLEL MASTER PORT(PMP)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 13. “ParallelMaster Port (PMP)” (DS39713) in the“PIC24F Family Reference Manual” formore information.The Parallel Master Port (PMP) module is a parallel,8-bit I/O module, specifically designed to communicatewith a wide variety of parallel devices, such as communicationperipherals, LCDs, external memory devicesand microcontrollers. Because the interface to parallelperipherals varies significantly, the PMP is highlyconfigurable.Key features of the PMP module include:• Up to 16 Programmable Address Lines• Up to Two Chip Select Lines• Programmable Strobe Options- Individual Read and Write Strobes or;- Read/Write Strobe with Enable Strobe• Address Auto-Increment/Auto-Decrement• Programmable Address/Data Multiplexing• Programmable Polarity on Control Signals• Legacy Parallel Slave Port Support• Enhanced Parallel Slave Support- Address Support- 4-Byte Deep Auto-Incrementing Buffer• Programmable Wait States• Selectable Input Voltage LevelsFIGURE 17-1:PMP MODULE OVERVIEWAddress BusData BusControl LinesPIC24FParallel Master PortPMAPMALLPMAPMALHPMAUp to 16-Bit AddressEEPROMPMAPMCS1PMAPMCS2PMBEPMRDPMRD/PMWRMicrocontrollerLCDFIFOBufferPMWRPMENBPMDPMAPMA8-Bit Data© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 147

PIC24FJ128GA010 FAMILYREGISTER 17-1:PMCON: PARALLEL PORT CONTROL REGISTERR/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDENbit 15 bit 8R/W-0 R/W-0 R/W-0 (1) R/W-0 (1) R/W-0 (1) R/W-0 R/W-0 R/W-0CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSPbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 PMPEN: Parallel Master Port Enable bit1 = PMP enabled0 = PMP disabled, no off-chip access performedbit 14 Unimplemented: Read as ‘0’bit 13bit 12-11bit 10bit 9bit 8PSIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modeADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits11 = Reserved10 = All 16 bits of address are multiplexed on PMD pins01 = Lower 8 bits of address are multiplexed on PMD pins, upper 8 bits are on PMA00 = Address and data appear on separate pinsPTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)1 = PMBE port enabled0 = PMBE port disabledPTWREN: Write Enable Strobe Port Enable bit1 = PMWR/PMENB port enabled0 = PMWR/PMENB port disabledPTRDEN: Read/Write Strobe Port Enable bit1 = PMRD/PMWR port enabled0 = PMRD/PMWR port disabledbit 7-6 CSF1:CSF0: Chip Select Function bits11 = Reserved10 = PMCS1 and PMCS2 function as chip select01 = PMCS2 functions as chip select, PMCS1 functions as address bit 1400 = PMCS1 and PMCS2 function as address bits 15 and 14bit 5 ALP: Address Latch Polarity bit (1)1 = Active-high (PMALL and PMALH)0 = Active-low (PMALL and PMALH)bit 4 CS2P: Chip Select 2 Polarity bit (1)1 = Active-high (PMCS2)0 = Active-low (PMCS2)bit 3 CS1P: Chip Select 1 Polarity bit (1)1 = Active-high (PMCS1/PMCS)0 = Active-low (PMCS1/PMCS)Note 1:These bits have no effect when their corresponding pins are used as address lines.DS39747E-page 148© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 17-1:PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)bit 2bit 1bit 0Note 1:BEP: Byte Enable Polarity bit1 = Byte enable active-high (PMBE)0 = Byte enable active-low (PMBE)WRSP: Write Strobe Polarity bitFor Slave modes and Master mode 2 (PMMODE = 00,01,10):1 = Write strobe active-high (PMWR)0 = Write strobe active-low (PMWR)For Master mode 1 (PMMODE = 11):1 = Enable strobe active-high (PMENB)0 = Enable strobe active-low (PMENB)RDSP: Read Strobe Polarity bitFor Slave modes and Master mode 2 (PMMODE = 00,01,10):1 = Read strobe active-high (PMRD)0 = Read strobe active-low (PMRD)For Master mode 1 (PMMODE = 11):1 = Read/write strobe active-high (PMRD/PMWR)0 = Read/write strobe active-low (PMRD/PMWR)These bits have no effect when their corresponding pins are used as address lines.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 149

PIC24FJ128GA010 FAMILYREGISTER 17-2:PMMODE: PARALLEL PORT MODE REGISTERR-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0WAITB1 (1) WAITB0 (1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 (1) WAITE0 (1)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14-13bit 12-11bit 10BUSY: Busy bit (Master mode only)1 = Port is busy (not useful when the processor stall is active)0 = Port is not busyIRQM1:IRQM0: Interrupt Request Mode bits11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) oron a read or write operation when PMA = 11 (Addressable PSP mode only)10 = No interrupt generated, processor stall activated01 = Interrupt generated at the end of the read/write cycle00 = No interrupt generatedINCM1:INCM0: Increment Mode bits11 = PSP read and write buffers auto-increment (Legacy PSP mode only)10 = Decrement ADDR by 1 every read/write cycle01 = Increment ADDR by 1 every read/write cycle00 = No increment or decrement of addressMODE16: 8/16-Bit Mode bit1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transferbit 9-8 MODE1:MODE0: Parallel Port Mode Select bits11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA and PMD)10 = Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA and PMD)01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD and PMA)00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD)bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits (1)11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY00 = Data wait of 1 TCY; multiplexed address phase of 1 TCYbit 5-2 WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits1111 = Wait of additional 15 TCY...0001 = Wait of additional 1 TCY0000 = No additional wait cycles (operation forced into one TCY)bit 1-0 WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits (1)11 = Wait of 4 TCY10 = Wait of 3 TCY01 = Wait of 2 TCY00 = Wait of 1 TCYNote 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.DS39747E-page 150© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 17-3: PMADDR: PARALLEL PORT ADDRESS REGISTER (1)R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CS2 CS1 ADDRbit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADDRbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14bit 13-0Note 1:CS2: Chip Select 2 bit1 = Chip select 2 is active0 = Chip select 2 is inactive (pin functions as PMA)CS1: Chip Select 1 bit1 = Chip select 1 is active0 = Chip select 1 is inactive (pin functions as PMA)ADDR13:ADDR0: Parallel Port Destination Address bitsPMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only inSlave modes, and as PMADDR only in Master modes.REGISTER 17-4:PMAEN: PARALLEL PORT ENABLE REGISTERR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14bit 13-2bit 1-0PTEN15:PTEN14: PMCSx Strobe Enable bits1 = PMA15 and PMA14 function as either PMA or PMCS2 and PMCS10 = PMA15 and PMA14 function as port I/OPTEN13:PTEN2: PMP Address Port Enable bits1 = PMA function as PMP address lines0 = PMA function as port I/OPTEN1:PTEN0: PMALH/PMALL Strobe Enable bits1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL0 = PMA1 and PMA0 pads functions as port I/O© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 151

PIC24FJ128GA010 FAMILYREGISTER 17-5:PMSTAT: PARALLEL PORT STATUS REGISTERR-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0IBF IBOV — — IB3F IB2F IB1F IB0Fbit 15 bit 8R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1OBE OBUF — — OB3E OB2E OB1E OB0Ebit 7 bit 0Legend:HS = Hardware Settable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15IBF: Input Buffer Full Status bit1 = All writable input buffer registers are full0 = Some or all of the writable input buffer registers are emptybit 14 IBOV: Input Buffer Overflow Status bit1 = A write attempt to a full input byte register occurred (must be cleared in software)0 = No overflow occurredbit 13-12 Unimplemented: Read as ‘0’bit 11-8bit 7IB3F:IB0F: Input Buffer n Status Full bit1 = Input buffer contains data that has not been read (reading buffer will clear this bit)0 = Input buffer does not contain any unread dataOBE: Output Buffer Empty Status bit1 = All readable output buffer registers are empty0 = Some or all of the readable output buffer registers are fullbit 6 OBUF: Output Buffer Underflow Status bit1 = A read occurred from an empty output byte register (must be cleared in software)0 = No underflow occurredbit 5-4 Unimplemented: Read as ‘0’bit 3-0 OB3E:OB0E: Output Buffer n Status Empty bit1 = Output buffer is empty (writing data to the buffer will clear this bit)0 = Output buffer contains data that has not been transmittedDS39747E-page 152© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 17-6:PADCFG1: PAD CONFIGURATION CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — RTSECSEL (1) PMPTTL (2)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-2 Unimplemented: Read as ‘0’bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit (1)1 = RTCC Seconds Clock is selected for the RTCC pin0 = RTCC Alarm Pulse is selected for the RTCC pinbit 0 PMPTTL: PMP Module TTL Input Buffer Select bit (2)1 = PMP module uses TTL input buffers0 = PMP module uses Schmitt input buffersNote 1: To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set.2: Refer to Table 1-2 for affected PMP inputs.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 153

PIC24FJ128GA010 FAMILYFIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLEMasterPMDPMCSPMRDPMWRPIC24F SlavePMDPMCSPMRDPMWRAddress BusData BusControl LinesFIGURE 17-3:ADDRESSABLE PARALLEL SLAVE PORT EXAMPLEMasterPMAPMAPIC24F SlavePMDPMDWriteAddressDecodeReadAddressDecodePMCSPMRDPMWRPMCSPMRDPMWRPMDOUT1L (0)PMDOUT1H (1)PMDOUT2L (2)PMDOUT2H (3)PMDIN1L (0)PMDIN1H (1)PMDIN2L (2)PMDIN2H (3)Address BusData BusControl LinesTABLE 17-1: SLAVE MODE ADDRESS RESOLUTIONPMA Output Register (Buffer) Input Register (Buffer)00 PMDOUT1 (0) PMDIN1 (0)01 PMDOUT1 (1) PMDIN1 (1)10 PMDOUT2 (2) PMDIN2 (2)11 PMDOUT2 (3) PMDIN2 (3)FIGURE 17-4:MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ ANDWRITE STROBES, TWO CHIP SELECTS)PIC24FPMAPMDPMCS1PMCS2PMRDPMWRAddress BusData BusControl LinesDS39747E-page 154© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 17-5:MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READAND WRITE STROBES, TWO CHIP SELECTS)PIC24FPMAPMDPMAPMCS1PMCS2PMALLPMRDPMWRAddress BusMultiplexedData andAddress BusControl LinesFIGURE 17-6:MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ ANDWRITE STROBES, TWO CHIP SELECTS)PIC24FPMDPMAPMCS1PMCS2PMALLPMALHPMRDPMWRMultiplexedData andAddress BusControl LinesFIGURE 17-7:EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATIONPIC24FPMDPMALL373ADADPMALH373ACEOEWRPMCS1PMRDPMWRAddress BusData BusControl LinesFIGURE 17-8:EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATIONPIC24FPMDPMALLPMAPMCS1PMRDPMWRA373ADADCEOE WRAddress BusData BusControl Lines© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 155

PIC24FJ128GA010 FAMILYFIGURE 17-9:EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATIONPIC24FPMDPMALLPMCS1PMRDPMWRParallel PeripheralADALECSRDWRAddress BusData BusControl LinesFIGURE 17-10:PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)PIC24FPMAPMDPMCS1PMRDPMWRParallel EEPROMADCEOEWRAddress BusData BusControl LinesFIGURE 17-11:PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)PIC24FPMAPMDPMBEPMCS1PMRDPMWRParallel EEPROMADA0CEOEWRAddress BusData BusControl LinesFIGURE 17-12:LCD CONTROL EXAMPLE (BYTE MODE OPERATION)PIC24FPMPMA0PMRD/PMWRPMCS1DRSR/WELCD ControllerAddress BusData BusControl LinesDS39747E-page 156© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY18.0 REAL-TIME CLOCK ANDCALENDAR (RTCC)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 29. “Real-TimeClock and Calendar (RTCC)” (DS39696)in the “PIC24F Family Reference Manual”for more information.The Real-Time Clock and Calendar hardware modulehas the following features:• Time: Hours, Minutes and Seconds• 24-Hour Format (Military Time)• Calendar: Weekday, Date, Month and Year• Alarm Configurable• Year Range: 2000 to 2099• Leap Year Correction• BCD Format for Compact Firmware• Optimized for Low-Power Operation• User Calibration with Auto-Adjust• Calibration Range: ±2.64 Seconds Error perMonth• Requirements: External 32.768 kHz Clock Crystal• Alarm Pulse or Seconds Clock Output on RTCCpinFIGURE 18-1:RTCC BLOCK DIAGRAMRTCC Clock DomainCPU Clock Domain32.768 kHz Inputfrom SOSC OscillatorAlarmEventRTCC Prescalers0.5sRTCC TimerComparatorRCFGCALALCFGRPTRTCVALYEARMTHDAYWKDYHRMINSECCompare Registerswith MasksALRMVALALMTHDYALWDHRALMINSECRepeat CounterRTCC Interrupt LogicRTCC InterruptAlarm PulseRTCC PinRTCOE© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 157

PIC24FJ128GA010 FAMILY18.1 RTCC Module RegistersThe RTCC module registers are organized into threecategories:• RTCC Control Registers• RTCC Value Registers• Alarm Value Registers18.1.1 REGISTER MAPPINGTo limit the register interface, the RTCC Timer andAlarm Time registers are accessed through correspondingregister pointers. The RTCC Value registerwindow (RTCVALH and RTCVALL) uses the RTCPTRbits (RCFGCAL) to select the desired Timerregister pair (see Table 18-1). By writing the RTCVALHbyte, the RTCC Pointer value, RTCPTR, decrementsby one until it reaches ‘00’. Once it reaches ‘00’,the MINUTES and SECONDS value will be accessiblethrough RTCVALH and RTCVALL until the pointervalue is manually changed.TABLE 18-1:RTCPTRRTCVAL REGISTER MAPPINGRTCC Value Register WindowRTCVALRTCVAL00 MINUTES SECONDS01 WEEKDAY HOURS10 MONTH DAY11 — YEARThe Alarm Value register window (ALRMVALH andALRMVALL) uses the ALRMPTR bits(ALCFGRPT) to select the desired Alarm registerpair (see Table 18-2).By writing the ALRMVALH byte, the Alarm Pointervalue, ALRMPTR, decrements by one until itreaches ‘00’. Once it reaches ‘00’, the ALRMMIN andALRMSEC value will be accessible throughALRMVALH and ALRMVALL until the pointer value ismanually changed.TABLE 18-2:ALRMPTRALRMVAL REGISTERMAPPINGConsidering that the 16-bit core does not distinguishbetween 8-bit and 16-bit read operations, the user mustbe aware that when reading either the ALRMVALH orALRMVALL bytes will decrement the ALRMPTRvalue. The same applies to the RTCVALH or RTCVALLbytes with the RTCPTR being decremented.Note:Alarm Value Register WindowALRMVALALRMVAL00 ALRMMIN ALRMSEC01 ALRMWD ALRMHR10 ALRMMNTH ALRMDAY11 — —This only applies to read operations andnot write operations.18.1.2 WRITE LOCKIn order to perform a write to any of the RTCC Timerregisters, the RTCWREN bit (RCFGCAL) must beset (refer to Example 18-1).EXAMPLE 18-1:SETTING THE RTCWREN BITasm volatile("disi #5");asm volatile("mov #0x55, w7");asm volatile("mov w7, _NVMKEY");asm volatile("mov #0xAA, w8");asm volatile("mov w8, _NVMKEY");asm volatile("bset _RCFGCAL, #13");//set the RTCWREN bitNote:To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear atany other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that the code in Example 18-1 befollowed.DS39747E-page 158© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY18.1.3 RTCC CONTROL REGISTERSREGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER (1)R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0RTCEN (2) — RTCWREN RTCSYNC HALFSEC (3) RTCOE RTCPTR1 RTCPTR0bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 RTCEN: RTCC Enable bit (2)1 = RTCC module is enabled0 = RTCC module is disabledbit 14 Unimplemented: Read as ‘0’bit 13RTCWREN: RTCC Value Registers Write Enable bit1 = RTCVALH and RTCVALL registers can be written to by the user0 = RTCVALH and RTCVALL registers are locked out from being written to by the userbit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover rippleresulting in an invalid data read. If the register is read twice and results in the same data, the data canbe assumed to be valid.0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripplebit 11 HALFSEC: Half-Second Status bit (3)bit 10bit 9-81 = Second half period of a second0 = First half period of a secondRTCOE: RTCC Output Enable bit1 = RTCC output enabled0 = RTCC output disabledRTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bitsPoints to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers;the RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’.RTCVAL:00 = MINUTES01 = WEEKDAY10 =MONTH11 = ReservedRTCVAL:00 = SECONDS01 =HOURS10 =DAY11 = YEARNote 1: The RCFGCAL Reset value is dependent on type of Reset.2: A write to the RTCEN bit is only allowed when RTCWREN = 1.3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 159

PIC24FJ128GA010 FAMILYREGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER (1)bit 7-0CAL7:CAL0: RTC Drift Calibration bits01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute...01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute00000000 = No adjustment11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute...10000000 =Maximum negative adjustment; subtracts 512 RTC clock pulses every one minuteNote 1: The RCFGCAL Reset value is dependent on type of Reset.2: A write to the RTCEN bit is only allowed when RTCWREN = 1.3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.REGISTER 18-2:PADCFG1: PAD CONFIGURATION CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0— — — — — — RTSECSEL (1) PMPTTL (2)bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-2 Unimplemented: Read as ‘0’bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit (1)1 = RTCC Seconds Clock is selected for the RTCC pin0 = RTCC Alarm Pulse is selected for the RTCC pinbit 0 PMPTTL: PMP Module TTL Input Buffer Select bit (2)1 = PMP module uses TTL input buffers0 = PMP module uses Schmitt input buffersNote 1: To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set.2: Refer to Table 1-2 for affected PMP inputs.DS39747E-page 160© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 18-3:ALCFGRPT: ALARM CONFIGURATION REGISTERR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15bit 14bit 13-10bit 9-8bit 7-0ALRMEN: Alarm Enable bit1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00 andCHIME = 0)0 = Alarm is disabledCHIME: Chime Enable bit1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh0 = Chime is disabled; ARPT bits stop once they reach 00hAMASK3:AMASK0: Alarm Mask Configuration bits0000 = Every half second0001 = Every second0010 = Every 10 seconds0011 = Every minute0100 = Every 10 minutes0101 = Every hour0110 = Once a day0111 = Once a week1000 = Once a month1001 = Once a year (except when configured for February 29th, once every 4 years)101x = Reserved – do not use11xx = Reserved – do not useALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bitsPoints to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;the ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’.ALRMVAL:00 =ALRMMIN01 =ALRMWD10 =ALRMMNTH11 = UnimplementedALRMVAL:00 = ALRMSEC01 =ALRMHR10 =ALRMDAY11 = UnimplementedARPT7:ARPT0: Alarm Repeat Counter Value bits11111111 = Alarm will repeat 255 more times...00000000 = Alarm will not repeatThe counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFhunless CHIME = 1.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 161

PIC24FJ128GA010 FAMILY18.1.4 RTCVAL REGISTER MAPPINGSREGISTER 18-4: YEAR: YEAR VALUE REGISTER (1)U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-xYRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-8 Unimplemented: Read as ‘0’bit 7-4 YRTEN3:YRTEN0: Binary Coded Decimal Value of Year’s Tens Digit; Contains a value from 0 to 9bit 3-0 YRONE3:YRONE0: Binary Coded Decimal Value of Year’s Ones Digit; Contains a value from 0 to 9Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.REGISTER 18-5: MTHDY: MONTH AND DAY VALUE REGISTER (1)U-0 U-0 U-0 R-x R-x R-x R-x R-x— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0bit 15 bit 8U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-13 Unimplemented: Read as ‘0’bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9bit 7-6 Unimplemented: Read as ‘0’bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9Note 1: A write to this register is only allowed when RTCWREN = 1.DS39747E-page 162© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 18-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER (1)U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x— — — — — WDAY2 WDAY1 WDAY0bit 15 bit 8U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-11 Unimplemented: Read as ‘0’bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6bit 7-6 Unimplemented: Read as ‘0’bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9Note 1: A write to this register is only allowed when RTCWREN = 1.REGISTER 18-7:MINSEC: MINUTES AND SECONDS VALUE REGISTERU-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0bit 15 bit 8U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9bit 7 Unimplemented: Read as ‘0’bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 163

PIC24FJ128GA010 FAMILY18.1.5 ALRMVAL REGISTER MAPPINGSREGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER (1)U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0bit 15 bit 8U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-13 Unimplemented: Read as ‘0’bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9bit 7-6 Unimplemented: Read as ‘0’bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9Note 1: A write to this register is only allowed when RTCWREN = 1.REGISTER 18-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER (1)U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x— — — — — WDAY2 WDAY1 WDAY0bit 15 bit 8U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-11 Unimplemented: Read as ‘0’bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6bit 7-6 Unimplemented: Read as ‘0’bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9Note 1: A write to this register is only allowed when RTCWREN = 1.DS39747E-page 164© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 18-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTERU-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0bit 15 bit 8U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 Unimplemented: Read as ‘0’bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9bit 7 Unimplemented: Read as ‘0’bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 165

PIC24FJ128GA010 FAMILY18.2 CalibrationThe real-time crystal input can be calibrated using theperiodic auto-adjust feature. When properly calibrated,the RTCC can provide an error of less than 3 secondsper month. This is accomplished by finding the numberof error clock pulses and storing the value into thelower half of the RCFGCAL register. The 8-bit signedvalue loaded into the lower half of RCFGCAL is multipliedby four and will be either added or subtracted fromthe RTCC timer, once every minute. Refer to the stepsbelow for RTCC calibration:1. Using another timer resource on the device, theuser must find the error of the 32.768 kHzcrystal.2. Once the error is known, it must be converted tothe number of error clock pulses per minute.EQUATION 18-1:(Ideal Frequency † – Measured Frequency) * 60 = Clocks per Minute3. a) If the oscillator is faster then ideal (negativeresult form step 2), the RCFGCAL register valueneeds to be negative. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.b) If the oscillator is slower then ideal (positiveresult from step 2), the RCFGCAL register valueneeds to be positive. This causes the specifiednumber of clock pulses to be subtracted fromthe timer counter once every minute.4. Divide the number of error clocks per minute by4 to get the correct CAL value and load theRCFGCAL register with the correct value. (Each1-bit increment in CAL adds or subtracts4 pulses). Load the RCFGCAL register with thecorrect value.Writes to the lower half of the RCFGCAL registershould only occur when the timer is turnedoff, or immediately after the rising edge of theseconds pulse.Note:† Ideal Frequency = 32,768 HzIt is up to the user to include in the errorvalue the initial error of the crystal, driftdue to temperature and drift due to crystalaging.18.3 Alarm• Configurable from half second to one year• Enabled using the ALRMEN bit(ALCFGRPT, Register 18-3)• One-time alarm and repeat alarm options available18.3.1 CONFIGURING THE ALARMThe alarm feature is enabled using the ALRMEN bit.This bit is cleared when an alarm is issued. Writes toALRMVALH:ALRMVALL should only take place whenALRMEN = 0.As shown in Figure 18-2, the interval selection of thealarm is configured through the AMASK bits(ALCFGRPT). These bits determine which andhow many digits of the alarm must match the clockvalue for the alarm to occur. The alarm can also be configuredto repeat based on a preconfigured interval.The amount of times this occurs once the alarm isenabled is stored in the lower half of the ALCFGRPTregister.When ALCFGRPT = 00 and the CHIME bit = 0(ALCFGRPT), the repeat function is disabled andonly a single alarm will occur. The alarm can berepeated up to 255 times by loading the lower half ofthe ALCFGRPT register with FFh.After each alarm is issued, the ALCFGRPT register isdecremented by one. Once the register has reached‘00’, the alarm will be issued one last time, after which,the ALRMEN bit will be cleared automatically and thealarm will turn off. Indefinite repetition of the alarm canoccur if the CHIME bit = 1. Instead of the alarm beingdisabled when the ALCFGRPT register reaches ‘00’, itwill roll over to FF and continue counting indefinitelywhen CHIME = 1.18.3.2 ALARM INTERRUPTAt every alarm event an interrupt is generated. In addition,an alarm pulse output is provided that operates athalf the frequency of the alarm. This output iscompletely synchronous to the RTCC clock and can beused as a trigger clock to other peripherals.Note:Changing any of the registers, other thenthe RCFGCAL and ALCFGRPT registersand the CHIME bit while the alarm isenabled (ALRMEN = 1), can result in afalse alarm event leading to a false alarminterrupt. To avoid a false alarm event, thetimer and alarm values should only bechanged while the alarm is disabled(ALRMEN = 0). It is recommended that theALCFGRPT register and CHIME bit bechanged when RTCSYNC = 0.DS39747E-page 166© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 18-2:ALARM MASK SETTINGSAlarm Mask Setting(AMASK3:AMASK0)0000 – Every half second0001 – Every second0010 – Every 10 secondsDay oftheWeek Month Day Hours Minutes Secondss0011 – Every minutess0100 – Every 10 minutesm s s0101 – Every hourm m s s0110 – Every dayh h m m s s0111 – Every weekd h h m m s s1000 – Every monthd d h h m m s s1001 – Every year (1)m m d d h h m m s sNote 1: Annually, except when configured for February 29.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 167

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 168© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY19.0 PROGRAMMABLE CYCLICREDUNDANCY CHECK (CRC)GENERATORNote:The programmable CRC generator offers the followingfeatures:• User-programmable polynomial CRC equation• Interrupt output• Data FIFO19.1 RegistersThis data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 30. “ProgrammableCyclic Redundancy Check(CRC)” (DS39714) in the “PIC24F FamilyReference Manual” for more information.There are four registers used to control programmableCRC operation:• CRCCON• CRCXOR• CRCDAT• CRCWDAT19.2 OverviewThe module implements a software configurable CRCgenerator. The terms of the polynomial and its lengthcan be programmed using the CRCXOR (X) bitsand the CRCCON (PLEN3:PLEN0) bits, respectively.Consider the following equation:EQUATION 19-1:CRC POLYNOMIALTo program this polynomial into the CRC generator,the CRC register bits should be set as shown inTable 19-1.TABLE 19-1:Bit Namex 16 + x 12 + x 5 + 1EXAMPLE CRC SETUPBit ValuePLEN3:PLEN0 1111X 000100000010000Note that for the value of X, the 12th bit and the5th bit are set to ‘1’, as required by the equation. The 0 bitrequired by the equation is always XORed. For a 16-bitpolynomial, the 16th bit is also always assumed to beXORed; therefore, the X bits do not have the 0 bitor the 16th bit.The topology of a standard CRC generator is shown inFigure 19-2.FIGURE 19-1:CRC SHIFTER DETAILSPLEN0 1 2 15CRC Shift RegisterHold X1 Hold X2 Hold X3 X15 HoldDOUTXOROUTINBIT 001OUTINBIT 101OUTINBIT 20101OUTINBIT 15p_clkp_clkp_clkp_clkCRC Read BusCRC Write Bus© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 169

PIC24FJ128GA010 FAMILYFIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x 16 + x 12 + x 5 + 1XORSDOxDBIT 0QDBIT 4QDBIT 5QDQBIT 12DBIT 15Qp_clkp_clkp_clkp_clkp_clkCRC Read BusCRC Write Bus19.3 User Interface19.3.1 DATA INTERFACETo start serial shifting, a ‘1’ must be written to theCRCGO bit.The module incorporates a FIFO that is 8 deep whenPLEN (PLEN) > 7, and 16 deep otherwise. Thedata for which the CRC is to be calculated must first bewritten into the FIFO. The smallest data element thatcan be written into the FIFO is one byte. For example,if PLEN = 5, then the size of the data is PLEN + 1 = 6.The data must be written as follows:data[5:0] = crc_input[5:0]data[7:6] = ‘bxxOnce data is written into the CRCWDAT MSb (asdefined by PLEN), the value of VWORD(VWORD) increments by one. The serial shifterstarts shifting data into the CRC engine whenCRCGO = 1 and VWORD > 0. When the MSb isshifted out, VWORD decrements by one. The serialshifter continues shifting until the VWORD reaches 0.Therefore, for a given value of PLEN, it will take(PLEN + 1) * VWORD number of clock cycles tocomplete the CRC calculations.When VWORD reaches 8 (or 16), the CRCFUL bit willbe set. When VWORD reaches 0, the CRCMPT bit willbe set.To continually feed data into the CRC engine, the recommendedmode of operation is to initially “prime” theFIFO with a sufficient number of words so no interruptis generated before the next word can be written. Oncethat is done, start the CRC by setting the CRCGO bit to‘1’. From that point onward, the VWORD bits should bepolled. If they read less than 8 or 16, another word canbe written into the FIFO.To empty words already written into a FIFO, theCRCGO bit must be set to ‘1’ and the CRC shifterallowed to run until the CRCMPT bit is set.Also, to get the correct CRC reading, it will benecessary to wait for the CRCMPT bit to go high beforereading the CRCWDAT register.If a word is written when the CRCFUL bit is set, theVWORD Pointer will roll over to 0. The hardware willthen behave as if the FIFO is empty. However, the conditionto generate an interrupt will not be met; therefore,no interrupt will be generated (see Section 19.3.2“Interrupt Operation”).At least one instruction cycle must pass after a write toCRCWDAT before a read of the VWORD bits is done.19.3.2 INTERRUPT OPERATIONWhen VWORD4:VWORD0 make a transition from avalue of ‘1’ to ‘0’, an interrupt will be generated.DS39747E-page 170© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 19-1:CRCCON: CRC CONTROL REGISTERU-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0— — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0bit 15 bit 8R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CRCFUL CRCMPT — CRCGO PLEN3 PLEN2 PLEN1 PLEN0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-14 Unimplemented: Read as ‘0’bit 13 CSIDL: CRC Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-8 VWORD4:VWORD0: Pointer Value bitsIndicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7,or 16 when PLEN3:PLEN0 ≤ 7.bit 7 CRCFUL: FIFO Full bit1 = FIFO is full0 = FIFO is not fullbit 6 CRCMPT: FIFO Empty bit1 = FIFO is empty0 = FIFO is not emptybit 5 Unimplemented: Read as ‘0’bit 4 CRCGO: Start CRC bit1 = Start CRC serial shifter0 = CRC serial shifter turned offbit 3-0 PLEN3:PLEN0: Polynomial Length bitsDenotes the length of the polynomial to be generated minus 1.19.4 Operation in Power Save Modes19.4.1 SLEEP MODEIf Sleep mode is entered while the module is operating,the module will be suspended in its current state untilclock execution resumes.19.4.2 IDLE MODETo continue full module operation in Idle mode, theCSIDL bit must be cleared prior to entry into the mode.If CSIDL = 1, the module will behave the same way asit does in Sleep mode; pending interrupt events will bepassed on, even though the module clocks are notavailable.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 171

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 172© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY20.0 10-BIT HIGH-SPEED A/DCONVERTERNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 17. “10-Bit A/DConverter” (DS39705) in the “PIC24FFamily Reference Manual” for moreinformation.The 10-bit A/D Converter has the following keyfeatures:• Successive Approximation (SAR) conversion• Conversion speeds of up to 500 ksps• Up to 16 analog input pins• External voltage reference input pins• Automatic Channel Scan mode• Selectable conversion trigger source• 16-word conversion result buffer• Selectable Buffer Fill modes• Four result alignment options• Operation during CPU Sleep and Idle modesDepending on the particular device pinout, the 10-bitA/D Converter can have up to 16 analog input pins,designated AN0 through AN15. In addition, there aretwo analog input pins for external voltage referenceconnections. These voltage reference inputs may beshared with other analog input pins. The actual numberof analog input pins and external voltage referenceinput configuration will depend on the specific device.Refer to the device data sheet for further details.A block diagram of the A/D Converter is shown inFigure 20-1.To perform an A/D conversion:1. Configure the A/D module:a) Select port pins as analog inputs(AD1PCFG).b) Select voltage reference source to matchexpected range on analog inputs(AD1CON2).c) Select the analog conversion clock tomatch desired data rate with processorclock (AD1CON3).d) Select the appropriate sample/conversionsequence (AD1CON1 andAD1CON3).e) Select how conversion results arepresented in the buffer (AD1CON1).f) Select interrupt rate (AD1CON2).g) Turn on A/D module (AD1CON1).2. Configure A/D interrupt (if required):a) Clear the AD1IF bit.b) Select A/D interrupt priority.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 173

PIC24FJ128GA010 FAMILYFigure 20-1:10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAMInternal Data BusAVDDVR SelectVR+VR- VR+DACVR-VINHVINLS/HAVSSVREF+VREF-AN0Comparator16AN1AN2VINH10-Bit SARConversion LogicAN3AN4MUX AData FormattingAN5AN6AN7VINLADC1BUF0:ADC1BUFFAN8AN9AN10AN11AN12MUX BVINHVINLAD1CON1AD1CON2AD1CON3AD1CHSAD1PCFGAD1CSSLAN13AN14AN15Sample ControlInput MUX ControlPin Config. ControlControl LogicConversion ControlDS39747E-page 174© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 20-1: AD1CON1: A/D CONTROL REGISTER 1R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0ADON — ADSIDL — — — FORM1 FORM0bit 15 bit 8R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/C-0, HCSSSRC2 SSRC1 SSRC0 — — ASAM SAMP DONEbit 7 bit 0Legend: C = Clearable bit HCS = Hardware Clearable/Settable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 ADON: A/D Operating Mode bit1 = A/D Converter module is operating0 = A/D Converter is offbit 14 Unimplemented: Read as ‘0’bit 13 ADSIDL: Stop in Idle Mode bit1 = Discontinue module operation when device enters Idle mode0 = Continue module operation in Idle modebit 12-10 Unimplemented: Read as ‘0’bit 9-8FORM1:FORM0: Data Output Format bits11 = Signed fractional (sddd dddd dd00 0000)10 = Fractional (dddd dddd dd00 0000)01 = Signed integer (ssss sssd dddd dddd)00 = Integer (0000 00dd dddd dddd)bit 7-5 SSRC2:SSRC0: Conversion Trigger Source Select bits111 = Internal counter ends sampling and starts conversion (auto-convert)110 = Reserved10x = Reserved011 = Reserved010 = Timer3 compare ends sampling and starts conversion001 = Active transition on INT0 pin ends sampling and starts conversion000 = Clearing SAMP bit ends sampling and starts conversionbit 4-3 Unimplemented: Read as ‘0’bit 2bit 1bit 0ASAM: A/D Sample Auto-Start bit1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set.0 = Sampling begins when SAMP bit is setSAMP: A/D Sample Enable bit1 = A/D sample/hold amplifier is sampling input0 = A/D sample/hold amplifier is holdingDONE: A/D Conversion Status bit1 = A/D conversion is done0 = A/D conversion is NOT done© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 175

PIC24FJ128GA010 FAMILYREGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0VCFG2 VCFG1 VCFG0 r — CSCNA — —bit 15 bit 8R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTSbit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-13VCFG2:VCFG0: Voltage Reference Configuration bits:VCFG2:VCFG0 VR+ VR-000 AVDD AVSS001 External VREF+ pin AVSS010 AVDD External VREF- pin011 External VREF+ pin External VREF- pin1xx AVDD AVSSbit 12 Reservedbit 11 Unimplemented: Read as ‘0’bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit1 = Scan inputs0 = Do not scan inputsbit 9-8 Unimplemented: Read as ‘0’bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1)1 = A/D is currently filling buffer 08-0F, user should access data in 00-070 = A/D is currently filling buffer 00-07, user should access data in 08-0Fbit 6 Unimplemented: Read as ‘0’bit 5-2 SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence.....0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence0000 = Interrupts at the completion of conversion for each sample/convert sequencebit 1 BUFM: Buffer Mode Select bit1 = Buffer configured as two 8-word buffers (ADC1BUFx and ADC1BUFx)0 = Buffer configured as one 16-word buffer (ADC1BUFx)bit 0 ALTS: Alternate Input Sample Mode Select bit1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX Ainput multiplexer settings for all subsequent samples0 = Always use MUX A input multiplexer settingsDS39747E-page 176© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 20-3: AD1CON3: A/D CONTROL REGISTER 3R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADRC — — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 ADRC: A/D Conversion Clock Source bit1 = A/D internal RC clock0 = Clock derived from system clockbit 14-13 Unimplemented: Read as ‘0’bit 12-8bit 7-0SAMC4:SAMC0: Auto-Sample Time bits11111 = 31 TAD·····00001 = 1 TAD00000 = 0 TAD (not recommended)ADCS7:ADCS0: A/D Conversion Clock Select bits11111111 = 256 • TCY······00000001 = 2 * TCY00000000 = TCY© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 177

PIC24FJ128GA010 FAMILYREGISTER 20-4:AD1CHS: A/D INPUT SELECT REGISTERR/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0CH0NB — — — CH0SB3 CH0SB2 CH0SB1 CH0SB0bit 15 bit 8R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0CH0NA — — — CH0SA3 CH0SA2 CH0SA1 CH0SA0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is VRbit14-12 Unimplemented: Read as ‘0’bit 11-8CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits1111 = Channel 0 positive input is AN151110 = Channel 0 positive input is AN14·····0001 = Channel 0 positive input is AN10000 = Channel 0 positive input is AN0bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit1 = Channel 0 negative input is AN10 = Channel 0 negative input is VRbit6-4 Unimplemented: Read as ‘0’bit 3-0 CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits1111 = Channel 0 positive input is AN151110 = Channel 0 positive input is AN14·····0001 = Channel 0 positive input is AN10000 = Channel 0 positive input is AN0DS39747E-page 178© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 20-5:AD1PCFG: A/D PORT CONFIGURATION REGISTERR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-0PCFG15:PCFG0: Analog Input Pin Configuration Control bits1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltageREGISTER 20-6:AD1CSSL: A/D INPUT SCAN SELECT REGISTERR/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-0CSSL15:CSSL0: A/D Input Pin Scan Selection bits1 = Corresponding analog channel selected for input scan0 = Analog channel omitted from input scan© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 179

PIC24FJ128GA010 FAMILYEQUATION 20-1: A/D CONVERSION CLOCK PERIOD (1)Note 1:TAD = TCY(ADCS + 1)ADCS = TAD – 1TCYBased on TCY = TOSC * 2; Doze mode and PLL are disabled.FIGURE 20-2:10-BIT A/D CONVERTER ANALOG INPUT MODELRsANxVDDVT = 0.6VRIC ≤ 250ΩSamplingSwitchRSSRSS ≤ 5 kΩ (Typical)VACPIN6-11 pF(Typical)VT = 0.6VILEAKAGE±500 nACHOLD= DAC capacitance= 4.4 pF (Typical)VSSLegend:CPINVTILEAKAGERICRSSCHOLD= Input Capacitance= Threshold Voltage= Leakage Current at the pin due tovarious junctions= Interconnect Resistance= Sampling Switch Resistance= Sample/Hold Capacitance (from DAC)Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.DS39747E-page 180© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYFIGURE 20-3:A/D TRANSFER FUNCTIONOutput Code(Binary (Decimal))11 1111 1111 (1023)11 1111 1110 (1022)10 0000 0011 (515)10 0000 0010 (514)10 0000 0001 (513)10 0000 0000 (512)01 1111 1111 (511)01 1111 1110 (510)01 1111 1101 (509)00 0000 0001 (1)00 0000 0000 (0)Voltage Level0VR-VR+ – VR-VR- +1024512*(VR+ – VR-)10241023*(VR+ – VR-)1024VR+(VINH – VINL)VR- +VR- +© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 181

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 182© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY21.0 COMPARATOR MODULE The analog comparator module contains twoNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 19. “ComparatorModule” (DS39710) in the “PIC24FFamily Reference Manual” for moreinformation.comparators that can be configured in a variety ofways. The inputs can be selected from the analoginputs multiplexed with I/O pins, as well as the on-chipvoltage reference. Block diagrams of the variouscomparator configurations are shown in Figure 21-1.FIGURE 21-1:COMPARATOR I/O OPERATING MODESC1NEGC1IN+C1IN-VIN-C1ENC1INVCMCONC1OUTC1IN+CVREFC1POSVIN+C1C1OUTENC2NEGC2IN+C2IN-VIN-C2ENC2INVCMCONC2OUTC2IN+CVREFC2POSVIN+C2C2OUTEN© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 183

PIC24FJ128GA010 FAMILYREGISTER 21-1:CMCON: COMPARATOR CONTROL REGISTERR/W-0 U-0 R/C-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTENbit 15 bit 8R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0C2OUT C1OUT C2INV C1INV C2NEG C2POS C1NEG C1POSbit 7 bit 0Legend:C = Clearable bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15 CMIDL: Stop in Idle Mode bit1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled.0 = Continue normal module operation in Idle modebit 14 Unimplemented: Read as ‘0’bit 13bit 12bit 11bit 10bit 9bit 8bit 7bit 6C2EVT: Comparator 2 Event bit1 = Comparator output changed states0 = Comparator output did not change statesC1EVT: Comparator 1 Event bit1 = Comparator output changed states0 = Comparator output did not change statesC2EN: Comparator 2 Enable bit1 = Comparator is enabled0 = Comparator is disabledC1EN: Comparator 1 Enable bit1 = Comparator is enabled0 = Comparator is disabledC2OUTEN: Comparator 2 Output Enable bit1 = Comparator output is driven on the output pad0 = Comparator output is not driven on the output padC1OUTEN: Comparator 1 Output Enable bit1 = Comparator output is driven on the output pad0 = Comparator output is not driven on the output padC2OUT: Comparator 2 Output bitWhen C2INV = 0:1 = C2 VIN+ > C2 VIN-0 = C2 VIN+ < C2 VIN-When C2INV = 1:0 = C2 VIN+ > C2 VIN-1 = C2 VIN+ < C2 VIN-C1OUT: Comparator 1 Output bitWhen C1INV = 0:1 = C1 VIN+ > C1 VIN-0 = C1 VIN+ < C1 VIN-When C1INV = 1:0 = C1 VIN+ > C1 VIN-1 = C1 VIN+ < C1 VIN-DS39747E-page 184© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 21-1:CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)bit 5bit 4bit 3bit 2bit 1bit 0C2INV: Comparator 2 Output Inversion bit1 = C2 output inverted0 = C2 output not invertedC1INV: Comparator 1 Output Inversion bit1 = C1 output inverted0 = C1 output not invertedC2NEG: Comparator 2 Negative Input Configure bit1 = Input is connected to VIN+0 = Input is connected to VIN-See Figure 21-1 for the Comparator modes.C2POS: Comparator 2 Positive Input Configure bit1 = Input is connected to VIN+0 = Input is connected to CVREFSee Figure 21-1 for the Comparator modes.C1NEG: Comparator 1 Negative Input Configure bit1 = Input is connected to VIN+0 = Input is connected to VIN-See Figure 21-1 for the Comparator modes.C1POS: Comparator 1 Positive Input Configure bit1 = Input is connected to VIN+0 = Input is connected to CVREFSee Figure 21-1 for the Comparator modes.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 185

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 186© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY22.0 COMPARATOR VOLTAGEREFERENCENote:This data sheet summarizes features ofPIC24F group of devices and is notintended to be a comprehensive referencesource. Refer to Section 20. “ComparatorVoltage Reference Module”(DS39709) in the “PIC24F FamilyReference Manual” for more information.22.1 Configuring the ComparatorVoltage ReferenceThe voltage reference module is controlled through theCVRCON register (Register 22-1). The comparatorvoltage reference provides two ranges of outputvoltage, each with 16 distinct levels. The range to beused is selected by the CVRR bit (CVRCON). Theprimary difference between the ranges is the size of thesteps selected by the CVREF Selection bits(CVR3:CVR0), with one range offering finer resolution.The comparator reference supply voltage can comefrom either VDD and VSS, or the external VREF+ andVREF-. The voltage source is selected by the CVRSSbit (CVRCON).The settling time of the comparator voltage referencemust be considered when changing the CVREFoutput.CVRR: Comparator VREF Range Selection bit 1 = 0to 0.625 CVRSRC, with CVRSRC/24 step size0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step sizeFIGURE 22-1:COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAMVREF+CVRSS = 1AVDDCVRSS = 08RCVR3:CVR0CVRENRRR16 StepsRR16-to-1 MUXCVREFRRCVRRVREF-CVRSS = 18RCVRSS = 0AVSS© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 187

PIC24FJ128GA010 FAMILYREGISTER 22-1:CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTERU-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —bit 15 bit 8R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0bit 7 bit 0Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 15-8 Unimplemented: Read as ‘0’bit 7 CVREN: Comparator Voltage Reference Enable bit1 = CVREF circuit powered on0 = CVREF circuit powered downbit 6 CVROE: Comparator VREF Output Enable bit1 = CVREF voltage level is output on CVREF pin0 = CVREF voltage level is disconnected from CVREF pinbit 5 CVRR: Comparator VREF Range Selection bit1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step sizebit 4 CVRSS: Comparator VREF Source Selection bit1 = Comparator reference source CVRSRC = VREF+ – VREF-0 = Comparator reference source CVRSRC = AVDD – AVSSbit 3-0CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bitsWhen CVRR = 1:CVREF = (CVR/ 24) • (CVRSRC)When CVRR = 0:CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC)DS39747E-page 188© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY23.0 SPECIAL FEATURESNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 32. “High-LevelDevice Integration” (DS39719) in the“PIC24F Family Reference Manual” formore information.PIC24FJ128GA010 devices include several featuresintended to maximize application flexibility and reliability,and minimize cost through elimination of externalcomponents. These are:• Flexible Configuration• Watchdog Timer (WDT)• Code Protection• JTAG Boundary Scan Interface• In-Circuit Serial Programming• In-Circuit Emulation23.1 Configuration BitsThe Configuration bits can be programmed (read as‘0’), or left unprogrammed (read as ‘1’), to select variousdevice configurations. These bits are mappedstarting at program memory location F80000h. A completelist is shown in Table 23-1. A detailed explanationof the various bit functions is provided in Register 23-1through Register 23-4.Note that address F80000h is beyond the user programmemory space. In fact, it belongs to the configurationmemory space (800000h-FFFFFFh) which can only beaccessed using table reads and table writes.TABLE 23-1:DeviceFLASH CONFIGURATIONWORDS LOCATIONSConfiguration WordAddresses1 2PIC24FJ64GA 00ABFEh 00ABFChPIC24FJ96GA 00FFFEh 00FFFChPIC24FJ128GA 0157FEh 0157FChWhen creating applications for these devices, usersshould always specifically allocate the location of theFlash Configuration Word for configuration data. This isto make certain that program code is not stored in thisaddress when the code is compiled.The Configuration bits are reloaded from the FlashConfiguration Word on any device Reset.The upper byte of both Flash Configuration Words inprogram memory should always be ‘1111 1111’. Thismakes them appear to be NOP instructions in theremote event that their locations are ever executed byaccident. Since Configuration bits are not implementedin the corresponding locations, writing ‘1’s to theselocations has no effect on device operation.23.1.1 CONSIDERATIONS FORCONFIGURING PIC24FJ128GA010FAMILY DEVICESIn PIC24FJ128GA010 <strong>family</strong> devices, the configurationbytes are implemented as volatile memory. This meansthat configuration data must be programmed each timethe device is powered up. Configuration data is storedin the two words at the top of the on-chip programmemory space, known as the Flash ConfigurationWords. Their specific locations are shown inTable 23-1. These are packed representations of theactual device Configuration bits, whose actuallocations are distributed among five locations in configurationspace. The configuration data is automaticallyloaded from the Flash Configuration Words to theproper Configuration registers during device Resets.Note: Configuration data is reloaded on all typesof device resets.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 189

PIC24FJ128GA010 FAMILYREGISTER 23-1: FLASH CONFIGURATION WORD 1U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1— — — — — — — —bit 23 bit 16r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 U-1 R/PO-1r JTAGEN (1) GCP GWRP DEBUG r — ICSbit 15 bit 8R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0bit 7 bit 0Legend:R = Readable bit PO = Program-Once bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 23-16 Unimplemented: Read as ‘1’bit 15 Reserved: Program as ‘0’. Read value unknown.bit 14 JTAGEN: JTAG Port Enable bit (1)bit 13bit 121 = JTAG port is enabled0 = JTAG port is disabledGCP: General Segment Program Memory Code Protection bit1 = Code protection is disabled0 = Code protection is enabled for the entire program memory spaceGWRP: General Segment Code Flash Write Protection bit1 = Writes to program memory are allowed0 = Writes to program memory are disabledbit 11 DEBUG: Background Debugger Enable bit1 = Device resets into Operational mode0 = Device resets into Debug modebit 10 Reserved: Program as ‘1’bit 9 Unimplemented: Read as ‘1’bit 8bit 7ICS: Emulator Pin Placement Select bit1 = Emulator/debugger uses EMUC2/EMUD20 = Emulator/debugger uses EMUC1/EMUD1FWDTEN: Watchdog Timer Enable bit1 = Watchdog Timer is enabled0 = Watchdog Timer is disabledbit 6 WINDIS: Windowed Watchdog Timer Disable bit1 = Standard Watchdog Timer enabled0 = Windowed Watchdog Timer enabled; FWDTEN must be ‘1’bit 5 Unimplemented: Read as ‘1’bit 4FWPSA: WDT Prescaler Ratio Select bit1 = Prescaler ratio of 1:1280 = Prescaler ratio of 1:32Note 1:JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit SerialProgramming (ICSP).DS39747E-page 190© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 23-1:FLASH CONFIGURATION WORD 1 (CONTINUED)bit 3-0Note 1:WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits1111 = 1:32,7681110 = 1:16,3841101 = 1:8,1921100 = 1:4,0961011 = 1:2,0481010 = 1:1,0241001 = 1:5121000 = 1:2560111 = 1:1280110 = 1:640101 = 1:320100 = 1:160011 = 1:80010 = 1:40001 = 1:20000 = 1:1JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit SerialProgramming (ICSP).© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 191

PIC24FJ128GA010 FAMILYREGISTER 23-2: FLASH CONFIGURATION WORD 2U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1— — — — — — — —bit 23 bit 16R/PO-1 U-1 U-1 U-1 U-1 R/PO-1 R/PO-1 R/PO-1IESO — — — — FNOSC2 FNOSC1 FNOSC0bit 15 bit 8R/PO-1 R/PO-1 R/PO-1 U-1 U-1 U-1 R/PO-1 R/PO-1FCKSM1 FCKSM0 OSCIOFCN — — — POSCMD1 POSCMD0bit 7 bit 0Legend:R = Readable bit PO = Program-Once bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 23-16 Unimplemented: Read as ‘1’bit 15 IESO: Internal External Switchover bit1 = IESO mode (Two-Speed Start-up) enabled0 = IESO mode (Two-Speed Start-up) disabledbit 14-11 Unimplemented: Read as ‘1’bit 10-8 FNOSC2:FNOSC0: Initial Oscillator Select bits111 = Fast RC Oscillator with Postscaler (FRCDIV)110 = Reserved101 = Low-Power RC Oscillator (LPRC)100 = Secondary Oscillator (SOSC)011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)010 = Primary Oscillator (XT, HS, EC)001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL)000 = Fast RC Oscillator (FRC)bit 7-6 FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits1x = Clock switching and Fail-Safe Clock Monitor are disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabledbit 5 OSCIOFCN: OSC2 Pin Configuration bitIf POSCMD1:POSCMD0 = 11 or 00:1 = OSC2/CLKO/RC15 functions as CLKO (FOSC/2)0 = OSC2/CLKO/RC15 functions as port I/O (RC15)If POSCMD1:POSCMD0 = 10 or 01:OSCIOFCN has no effect on OSC2/CLKO/RC15.bit 4-2 Unimplemented: Read as ‘1’bit 1-0 POSCMD1:POSCMD0: Primary Oscillator Configuration bits11 = Primary oscillator disabled10 = HS Oscillator mode selected01 = XT Oscillator mode selected00 = EC Oscillator mode selectedDS39747E-page 192© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYREGISTER 23-3:DEVID: DEVICE ID REGISTERU U U U U U U U— — — — — — — —bit 23 bit 16U U R R R R R R— — FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2bit 15 bit 8R R R R R R R RFAMID1 FAMID0 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0bit 7 bit 0Legend:R = Readable bit PO = Program-Once bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 23-14 Unimplemented: Read as ‘0’bit 13-6 FAMID7:FAMID0: Device Family Identifier bits00010000 = PIC24FJ128GA010 <strong>family</strong>bit 5-0 DEV5:DEV0: Individual Device Identifier bits000101 = PIC24FJ64GA006000110 = PIC24FJ96GA006000111 = PIC24FJ128GA006001000 = PIC24FJ64GA008001001 = PIC24FJ96GA008001010 = PIC24FJ128GA008001011 = PIC24FJ64GA010001100 = PIC24FJ96GA010001101 = PIC24FJ128GA010© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 193

PIC24FJ128GA010 FAMILYREGISTER 23-4:DEVREV: DEVICE REVISION REGISTERU U U U U U U U— — — — — — — —bit 23 bit 16R R R R U U U Rr r r r — — — MAJRV2bit 15 bit 8R R U U U R R RMAJRV1 MAJRV0 — — — DOT2 DOT1 DOT0bit 7 bit 0Legend:R = Readable bit PO = Program-Once bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownbit 23-16 Unimplemented: Read as ‘0’bit 15-12 Reserved: For factory use onlybit 11-9 Unimplemented: Read as ‘0’bit 8-6 MAJRV2:MAJRV0: Major Revision Identifier bitsbit 5-3 Unimplemented: Read as ‘0’bit 2-0 DOT2:DOT0: Minor Revision Identifier bitsDS39747E-page 194© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY23.2 On-Chip Voltage RegulatorAll of the PIC24FJ128GA010 <strong>family</strong> devices powertheir core digital logic at a nominal 2.5V. This maycreate an issue for designs that are required to operateat a higher typical voltage, such as 3.3V. To simplifysystem design, all devices in the PIC24FJ128GA010incorporate an on-chip regulator that allows the deviceto run its core logic from VDD.The regulator is controlled by the ENVREG pin. TyingVDD to the pin enables the regulator, which in turn,provides power to the core from the other VDD pins.When the regulator is enabled, a low ESR capacitor(such as tantalum) must be connected to theVDDCORE/VCAP pin (Figure 23-1). This helps to maintainthe stability of the regulator. The recommendedvalue for the filer capacitor, CEFC, is provided inSection 26.1 “DC Characteristics”.If ENVREG is tied to VSS, the regulator is disabled. Inthis case, separate power for the core logic at a nominal2.5V must be supplied to the device on theVDDCORE/VCAP pin to run the I/O pins at higher voltagelevels, typically 3.3V. Alternatively, the VDDCORE/VCAPand VDD pins can be tied together to operate at a lowernominal voltage. Refer to Figure 23-1 for possibleconfigurations.23.2.1 ON-CHIP REGULATOR AND PORWhen the voltage regulator is enabled, it takes approximately20 μs for it to generate output. During this time,designated as TSTARTUP, code execution is disabled.TSTARTUP is applied every time the device resumesoperation after any power-down, including Sleep mode.If the regulator is disabled, a separate Power-up Timer(PWRT) is automatically enabled. The PWRT adds afixed delay of 64 ms nominal delay at device start-up.23.2.2 ON-CHIP REGULATOR AND BORWhen the on-chip regulator is enabled,PIC24FJ128GA010 devices also have a simplebrown-out capability. If the voltage supplied to the regulatoris inadequate to maintain a regulated level, theregulator Reset circuitry will generate a Brown-outReset. This event is captured by the BOR flag bit(RCON). The brown-out voltage specifications canbe found in the PIC24F Family Reference ManualReset chapter (DS39712).FIGURE 23-1:CONNECTIONS FOR THEON-CHIP REGULATORRegulator Enabled (ENVREG tied to VDD):3.3VPIC24FJ128GA010VDDENVREGVDDCORE/VCAPCEFCVSS(10 μF typ)Regulator Disabled (ENVREG tied to ground):2.5V (1) 3.3V (1)PIC24FJ128GA010VDDENVREGVDDCORE/VCAPVSSRegulator Disabled (VDD tied to VDDCORE):2.5V (1)PIC24FJ128GA010VDDENVREGVDDCORE/VCAPVSSNote 1: These are typical operating voltages. Referto Section 26.1 “DC Characteristics” forthe full operating ranges of VDD andVDDCORE.23.2.3 POWER-UP REQUIREMENTSThe on-chip regulator is designed to meet the power-uprequirements for the device. If the application does notuse the regulator, then strict power-up conditions mustbe adhered to. While powering up, VDDCORE mustnever exceed VDD by 0.3 volts.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 195

PIC24FJ128GA010 FAMILY23.3 Watchdog Timer (WDT)Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 9. “WatchdogTimer (WDT)” (DS39697) in the “PIC24FFamily Reference Manual” for moreinformation.For PIC24FJ128GA010 <strong>family</strong> devices, the WDT isdriven by the LPRC oscillator. When the WDT isenabled, the clock source is also enabled.The nominal WDT clock source from LPRC is 32 kHz.This feeds a prescaler that can be configured for either5-bit (divide-by-32) or 7-bit (divide-by-128) operation.The prescaler is set by the FWPSA Configuration bit.With a 32 kHz input, the prescaler yields a nominalWDT time-out period (TWDT) of 1 ms in 5-bit mode, or4 ms in 7-bit mode.A variable postscaler divides down the WDT prescaleroutput and allows for a wide range of time-out periods.The postscaler is controlled by the WDTPS3:WDTPS0Configuration bits (Flash Configuration Word 1),which allow the selection of a total of 16 settings, from1:1 to 1:32,768. Using the prescaler and postscaler,time-out periods ranging from 1 ms to 131 seconds canbe achieved.The WDT, prescaler and postscaler are reset:• On any device Reset• On the completion of a clock switch, whetherinvoked by software (i.e., setting the OSWEN bitafter changing the NOSC bits), or by hardware(i.e., Fail-Safe Clock Monitor)• When a PWRSAV instruction is executed (i.e.,Sleep or Idle mode is entered)• When the device exits Sleep or Idle mode toresume normal operation• By a CLRWDT instruction during normal executionIf the WDT is enabled, it will continue to run duringSleep or Idle modes. When the WDT time-out occurs,the device will wake the device and code execution willcontinue from where the PWRSAV instruction was executed.The corresponding SLEEP or IDLE bits(RCON) will need to be cleared in software afterthe device wakes up.The WDT Flag bit, WDTO (RCON), is not automaticallycleared following a WDT time-out. To detectsubsequent WDT events, the flag must be cleared insoftware.Note:The CLRWDT and PWRSAV instructionsclear the prescaler and postscaler countswhen executed.23.3.1 CONTROL REGISTERThe WDT is enabled or disabled by the FWDTENdevice Configuration bit. When the FWDTENConfiguration bit is set, the WDT is always enabled.The WDT can be optionally controlled in software whenthe FWDTEN Configuration bit has been programmedto ‘0’. The WDT is enabled in software by setting theSWDTEN control bit (RCON). The SWDTEN controlbit is cleared on any device Reset. The softwareWDT option allows the user to enable the WDT for criticalcode segments and disable the WDT duringnon-critical segments for maximum power savings.FIGURE 23-2:WDT BLOCK DIAGRAMSWDTENFWDTENLPRC ControlWake from SleepFWPSAWDTPS3:WDTPS0LPRC Input32 kHzPrescalerWDTPostscaler(5-bit/7-bit) Counter 1:1 to 1:32.7681 ms/4 msWDT OverflowResetAll Device ResetsTransition toNew Clock SourceExit Sleep orIdle ModeCLRWDT Instr.PWRSAV Instr.Sleep or Idle ModeDS39747E-page 196© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY23.4 JTAG Interface23.6 In-Circuit Serial ProgrammingNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 33. “Programmingand Diagnostics” (DS39716) in the“PIC24F Family Reference Manual” formore information.Note:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 33. “Programmingand Diagnostics” (DS39716) in the“PIC24F Family Reference Manual” formore information.PIC24FJ128GA010 <strong>family</strong> devices implement a JTAGinterface, which supports boundary scan device testingas well as in-circuit programming.Refer to the <strong>Microchip</strong> web site (www.microchip.com)for JTAG support files and additional information.23.5 Program Verification andCode ProtectionNote:This data sheet summarizes the featuresof this group of PIC24F devices. It is notintended to be a comprehensive referencesource. Refer to Section 33. “Programmingand Diagnostics” (DS39716) in the“PIC24F Family Reference Manual” formore information.For all devices in the PIC24FJ128GA010 <strong>family</strong> ofdevices, the on-chip program memory space is treatedas a single block. Code protection for this block is controlledby one Configuration bit, GCP. This bit inhibitsexternal reads and writes to the program memoryspace. It has no direct effect in normal execution mode.Write protection is controlled by the GWRP bit in theConfiguration Word. When GWRP is programmed to 0,internal write and erase operations to program memoryare blocked.PIC24FJ128GA010 <strong>family</strong> microcontrollers can beserially programmed while in the end application circuit.This is simply done with two lines for clock (PGCx) anddata (PGDx) and three other lines for power, groundand the programming voltage. This allows customers tomanufacture boards with unprogrammed devices andthen program the microcontroller just before shippingthe product. This also allows the most recent firmwareor a custom firmware to be programmed.23.7 In-Circuit DebuggerWhen MPLAB ® ICD 2 is selected as a debugger, theIn-Circuit Debugging functionality is enabled. Thisfunction allows simple debugging functions when usedwith MPLAB IDE. Debugging functionality is controlledthrough the EMUCx (Emulation/Debug Clock) andEMUDx (Emulation/Debug Data) pins.To use the In-Circuit Debugger function of the device,the design must implement ICSP connections toMCLR, VDD, VSS, PGCx, PGDx and theEMUDx/EMUCx pin pair. In addition, when the featureis enabled, some of the resources are not available forgeneral use. These resources include the first 80 bytesof data RAM and two I/O pins.23.5.1 CONFIGURATION REGISTERPROTECTIONThe Configuration registers are protected againstinadvertent or unwanted changes or reads in two ways.The primary protection method is the same as that ofthe shadow registers which contain a complimentaryvalue which is constantly compared with the actualvalue. To safeguard against unpredictable events, Configurationbit changes resulting from individual cell leveldisruptions (such as ESD events) will cause a parityerror and trigger a device Configuration Word MismatchReset.The data for the Configuration registers is derived fromthe Flash Configuration Words in program memory.When the GCP bit is set, the source data for deviceconfiguration is also protected as a consequence.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 197

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 198© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY24.0 INSTRUCTION SET SUMMARYThe PIC24F instruction set adds many enhancementsto the previous PIC ® MCU instruction sets, while maintainingan easy migration from previous PIC MCUinstruction sets. Most instructions are a single programmemory word. Only three instructions require twoprogram memory locations.Each single-word instruction is a 24-bit word dividedinto an 8-bit opcode, which specifies the instructiontype and one or more operands, which further specifythe operation of the instruction. The instruction set ishighly orthogonal and is grouped into four basiccategories:• Word or byte-oriented operations• Bit-oriented operations• Literal operations• Control operationsTable 24-1 shows the general symbols used indescribing the instructions. The PIC24F instruction setsummary in Table 24-2 lists all the instructions, alongwith the status flags affected by each instruction.Most word or byte-oriented W register instructions(including barrel shift instructions) have threeoperands:• The first source operand which is typically aregister ‘Wb’ without any address modifier• The second source operand which is typically aregister ‘Ws’ with or without an address modifier• The destination of the result which is typically aregister ‘Wd’ with or without an address modifierHowever, word or byte-oriented file register instructionshave two operands:• The file register specified by the value ‘f’• The destination, which could either be the fileregister ‘f’ or the W0 register, which is denoted as‘WREG’Most bit-oriented instructions (including simple rotate/shift instructions) have two operands:• The W register (with or without an addressmodifier) or file register (specified by the value of‘Ws’ or ‘f’)• The bit in the W register or file register(specified by a literal value or indirectly by thecontents of register ‘Wb’)The literal instructions that involve data movement mayuse some of the following operands:• A literal value to be loaded into a W register or fileregister (specified by the value of ‘k’)• The W register or file register where the literalvalue is to be loaded (specified by ‘Wb’ or ‘f’)However, literal instructions that involve arithmetic orlogical operations use some of the following operands:• The first source operand which is a register ‘Wb’without any address modifier• The second source operand which is a literalvalue• The destination of the result (only if not the sameas the first source operand) which is typically aregister ‘Wd’ with or without an address modifierThe control instructions may use some of the followingoperands:• A program memory address• The mode of the table read and table writeinstructionsAll instructions are a single word, except for certaindouble-word instructions, which were made doublewordinstructions so that all the required information isavailable in these 48 bits. In the second word, the8MSbs are ‘0’s. If this second word is executed as aninstruction (by itself), it will execute as a NOP.Most single-word instructions are executed in a singleinstruction cycle, unless a conditional test is true or theprogram counter is changed as a result of the instruction.In these cases, the execution takes two instructioncycles, with the additional instruction cycle(s) executedas a NOP. Notable exceptions are the BRA (unconditional/computedbranch), indirect CALL/GOTO, all tablereads and writes, and RETURN/RETFIE instructions,which are single-word instructions but take two or threecycles.Certain instructions that involve skipping over the subsequentinstruction require either two or three cycles ifthe skip is performed, depending on whether theinstruction being skipped is a single-word or two-wordinstruction. Moreover, double-word moves require twocycles. The double-word instructions execute in twoinstruction cycles.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 199

PIC24FJ128GA010 FAMILYTABLE 24-1:FieldSYMBOLS USED IN OPCODE DESCRIPTIONSDescription#textMeans literal defined by “text”(text)Means “content of text”[text]Means “the location addressed by text”{ } Optional field or operationRegister bit field.b Byte mode selection.d Double-Word mode selection.S Shadow register select.w Word mode selection (default)bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15}C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky ZeroExprAbsolute address, label or expression (resolved by the linker)fFile register address ∈ {0000h...1FFFh}lit1 1-bit unsigned literal ∈ {0,1}lit4 4-bit unsigned literal ∈ {0...15}lit5 5-bit unsigned literal ∈ {0...31}lit8 8-bit unsigned literal ∈ {0...255}lit1010-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word modelit14 14-bit unsigned literal ∈ {0...16384}lit16 16-bit unsigned literal ∈ {0...65535}lit23 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’NoneField does not require an entry, may be blankPCProgram CounterSlit10 10-bit signed literal ∈ {-512...511}Slit16 16-bit signed literal ∈ {-32768...32767}Slit6 6-bit signed literal ∈ {-16...16}WbBase W register ∈ {W0..W15}Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }WdoDestination W register ∈{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }Wm,WnDividend, Divisor working register pair (Direct Addressing)WnOne of 16 working registers ∈ {W0..W15}WndOne of 16 destination working registers ∈ {W0..W15}WnsOne of 16 source working registers ∈ {W0..W15}WREGW0 (working register used in file register instructions)Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }WsoSource W register ∈{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }DS39747E-page 200© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 24-2:AssemblyMnemonicINSTRUCTION SET OVERVIEWAssembly SyntaxDescription# ofWords# ofCyclesStatus FlagsAffectedADD ADD f f = f + WREG 1 1 C, DC, N, OV, ZADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, ZADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, ZADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, ZADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, ZADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, ZADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, ZADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, ZADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, ZADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, ZAND AND f f = f .AND. WREG 1 1 N, ZAND f,WREG WREG = f .AND. WREG 1 1 N, ZAND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, ZAND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, ZAND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, ZASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, ZASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, ZASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, ZASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, ZASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, ZBCLR BCLR f,#bit4 Bit Clear f 1 1 NoneBCLR Ws,#bit4 Bit Clear Ws 1 1 NoneBRA BRA C,Expr Branch if Carry 1 1 (2) NoneBRA GE,Expr Branch if Greater than or Equal 1 1 (2) NoneBRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) NoneBRA GT,Expr Branch if Greater than 1 1 (2) NoneBRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) NoneBRA LE,Expr Branch if Less than or Equal 1 1 (2) NoneBRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) NoneBRA LT,Expr Branch if Less than 1 1 (2) NoneBRA LTU,Expr Branch if Unsigned Less than 1 1 (2) NoneBRA N,Expr Branch if Negative 1 1 (2) NoneBRA NC,Expr Branch if Not Carry 1 1 (2) NoneBRA NN,Expr Branch if Not Negative 1 1 (2) NoneBRA NOV,Expr Branch if Not Overflow 1 1 (2) NoneBRA NZ,Expr Branch if Not Zero 1 1 (2) NoneBRA OV,Expr Branch if Overflow 1 1 (2) NoneBRA Expr Branch Unconditionally 1 2 NoneBRA Z,Expr Branch if Zero 1 1 (2) NoneBRA Wn Computed Branch 1 2 NoneBSET BSET f,#bit4 Bit Set f 1 1 NoneBSET Ws,#bit4 Bit Set Ws 1 1 NoneBSW BSW.C Ws,Wb Write C bit to Ws 1 1 NoneBSW.Z Ws,Wb Write Z bit to Ws 1 1 NoneBTG BTG f,#bit4 Bit Toggle f 1 1 NoneBTG Ws,#bit4 Bit Toggle Ws 1 1 NoneBTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1(2 or 3)BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1(2 or 3)NoneNone© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 201

PIC24FJ128GA010 FAMILYTABLE 24-2:INSTRUCTION SET OVERVIEW (CONTINUED)AssemblyMnemonicAssembly SyntaxDescription# ofWords# ofCyclesStatus FlagsAffectedBTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None(2 or 3)BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None(2 or 3)BTST BTST f,#bit4 Bit Test f 1 1 ZBTST.C Ws,#bit4 Bit Test Ws to C 1 1 CBTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 ZBTST.C Ws,Wb Bit Test Ws to C 1 1 CBTST.Z Ws,Wb Bit Test Ws to Z 1 1 ZBTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 ZBTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 CBTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 ZCALL CALL lit23 Call Subroutine 2 2 NoneCALL Wn Call Indirect Subroutine 1 2 NoneCLR CLR f f = 0x0000 1 1 NoneCLR WREG WREG = 0x0000 1 1 NoneCLR Ws Ws = 0x0000 1 1 NoneCLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, SleepCOM COM f f = f 1 1 N, ZCOM f,WREG WREG = f 1 1 N, ZCOM Ws,Wd Wd = Ws 1 1 N, ZCP CP f Compare f with WREG 1 1 C, DC, N, OV, ZCP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, ZCP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, ZCP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, ZCP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, ZCPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, ZCPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, ZCPB Wb,Ws Compare Wb with Ws, with Borrow1 1 C, DC, N, OV, Z(Wb – Ws – C)CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None(2 or 3)CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None(2 or 3)CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None(2 or 3)CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if ≠ 1 1 None(2 or 3)DAW DAW Wn Wn = Decimal Adjust Wn 1 1 CDEC DEC f f = f –1 1 1 C, DC, N, OV, ZDEC f,WREG WREG = f –1 1 1 C, DC, N, OV, ZDEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, ZDEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, ZDEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, ZDEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, ZDISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 NoneDIV DIV.SW Wm,Wn Signed 16/16-Bit Integer Divide 1 18 N, Z, C, OVDIV.SD Wm,Wn Signed 32/16-Bit Integer Divide 1 18 N, Z, C, OVDIV.UW Wm,Wn Unsigned 16/16-Bit Integer Divide 1 18 N, Z, C, OVDIV.UD Wm,Wn Unsigned 32/16-Bit Integer Divide 1 18 N, Z, C, OVEXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 NoneFF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 CFF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 CDS39747E-page 202© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 24-2:AssemblyMnemonicINSTRUCTION SET OVERVIEW (CONTINUED)Assembly SyntaxDescription# ofWords# ofCyclesStatus FlagsAffectedGOTO GOTO Expr Go to Address 2 2 NoneGOTO Wn Go to Indirect 1 2 NoneINC INC f f = f + 1 1 1 C, DC, N, OV, ZINC f,WREG WREG = f + 1 1 1 C, DC, N, OV, ZINC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, ZINC2 INC2 f f = f + 2 1 1 C, DC, N, OV, ZINC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, ZINC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, ZIOR IOR f f = f .IOR. WREG 1 1 N, ZIOR f,WREG WREG = f .IOR. WREG 1 1 N, ZIOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, ZIOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, ZIOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, ZLNK LNK #lit14 Link Frame Pointer 1 1 NoneLSR LSR f f = Logical Right Shift f 1 1 C, N, OV, ZLSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, ZLSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, ZLSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, ZLSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, ZMOV MOV f,Wn Move f to Wn 1 1 NoneMOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 NoneMOV f Move f to f 1 1 N, ZMOV f,WREG Move f to WREG 1 1 N, ZMOV #lit16,Wn Move 16-Bit Literal to Wn 1 1 NoneMOV.b #lit8,Wn Move 8-Bit Literal to Wn 1 1 NoneMOV Wn,f Move Wn to f 1 1 NoneMOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1MOV Wso,Wdo Move Ws to Wd 1 1 NoneMOV WREG,f Move WREG to f 1 1 N, ZMOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 NoneMOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 NoneMUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 NoneMUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 NoneMUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 NoneMUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 NoneMUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 NoneMUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 NoneMUL f W3:W2 = f * WREG 1 1 NoneNEG NEG f f = f + 1 1 1 C, DC, N, OV, ZNEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, ZNEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, ZNOP NOP No Operation 1 1 NoneNOPR No Operation 1 1 NonePOP POP f Pop f from Top-of-Stack (TOS) 1 1 NonePOP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 NonePOP.D Wnd Pop from Top-of-Stack (TOS) to1 2 NoneW(nd):W(nd+1)POP.S Pop Shadow Registers 1 1 AllPUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 NonePUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 NonePUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 NonePUSH.S Push Shadow Registers 1 1 None© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 203

PIC24FJ128GA010 FAMILYTABLE 24-2:AssemblyMnemonicINSTRUCTION SET OVERVIEW (CONTINUED)Assembly SyntaxDescription# ofWords# ofCyclesStatus FlagsAffectedPWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, SleepRCALL RCALL Expr Relative Call 1 2 NoneRCALL Wn Computed Call 1 2 NoneREPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 NoneREPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 NoneRESET RESET Software Device Reset 1 1 NoneRETFIE RETFIE Return from Interrupt 1 3 (2) NoneRETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) NoneRETURN RETURN Return from Subroutine 1 3 (2) NoneRLC RLC f f = Rotate Left through Carry f 1 1 C, N, ZRLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, ZRLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, ZRLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, ZRLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, ZRLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, ZRRC RRC f f = Rotate Right through Carry f 1 1 C, N, ZRRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, ZRRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, ZRRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, ZRRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, ZRRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, ZSE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, ZSETM SETM f f = FFFFh 1 1 NoneSETM WREG WREG = FFFFh 1 1 NoneSETM Ws Ws = FFFFh 1 1 NoneSL SL f f = Left Shift f 1 1 C, N, OV, ZSL f,WREG WREG = Left Shift f 1 1 C, N, OV, ZSL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, ZSL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, ZSL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, ZSUB SUB f f = f – WREG 1 1 C, DC, N, OV, ZSUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, ZSUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, ZSUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, ZSUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, ZSUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, ZSUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, ZSUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, ZSUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, ZSUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, ZSUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, ZSUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, ZSUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, ZSUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, ZSUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, ZSUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, ZSUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, ZSUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, ZSWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 NoneSWAP Wn Wn = Byte Swap Wn 1 1 NoneTBLRDH TBLRDH Ws,Wd Read Prog to Wd 1 2 NoneDS39747E-page 204© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 24-2:AssemblyMnemonicINSTRUCTION SET OVERVIEW (CONTINUED)Assembly SyntaxDescription# ofWords# ofCyclesTBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 NoneTBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 NoneTBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 NoneULNK ULNK Unlink Frame Pointer 1 1 NoneXOR XOR f f = f .XOR. WREG 1 1 N, ZXOR f,WREG WREG = f .XOR. WREG 1 1 N, ZXOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, ZXOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, ZXOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, ZZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, NStatus FlagsAffected© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 205

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 206© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY25.0 DEVELOPMENT SUPPORTThe PIC ® microcontrollers and dsPIC ® digital signalcontrollers are supported with a full range of softwareand hardware development tools:• Integrated Development Environment- MPLAB ® IDE Software• Compilers/Assemblers/Linkers- MPLAB C Compiler for Various DeviceFamilies- HI-TECH C for Various Device Families- MPASM TM Assembler- MPLINK TM Object Linker/MPLIB TM Object Librarian- MPLAB Assembler/Linker/Librarian forVarious Device Families• Simulators- MPLAB SIM Software Simulator• Emulators- MPLAB REAL ICE In-Circuit Emulator• In-Circuit Debuggers- MPLAB ICD 3- PICkit 3 Debug Express• Device Programmers- PICkit 2 Programmer- MPLAB PM3 Device Programmer• Low-Cost Demonstration/Development Boards,Evaluation Kits, and Starter Kits25.1 MPLAB Integrated DevelopmentEnvironment SoftwareThe MPLAB IDE software brings an ease of softwaredevelopment previously unseen in the 8/16/32-bitmicrocontroller market. The MPLAB IDE is a Windows ®operating system-based application that contains:• A single graphical interface to all debugging tools- Simulator- Programmer (sold separately)- In-Circuit Emulator (sold separately)- In-Circuit Debugger (sold separately)• A full-featured editor with color-coded context• A multiple project manager• Customizable data windows with direct edit ofcontents• High-level source code debugging• Mouse over variable inspection• Drag and drop variables from source to watchwindows• Extensive on-line help• Integration of select third party tools, such asIAR C CompilersThe MPLAB IDE allows you to:• Edit your source files (either C or assembly)• One-touch compile or assemble, and download toemulator and simulator tools (automaticallyupdates all project information)• Debug using:- Source files (C or assembly)- Mixed C and assembly- Machine codeMPLAB IDE supports multiple debugging tools in asingle development paradigm, from the cost-effectivesimulators, through low-cost in-circuit debuggers, tofull-featured emulators. This eliminates the learningcurve when upgrading to tools with increased flexibilityand power.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 207

PIC24FJ128GA010 FAMILY25.2 MPLAB C Compilers for VariousDevice FamiliesThe MPLAB C Compiler code development systemsare complete ANSI C compilers for <strong>Microchip</strong>’s PIC18,PIC24 and PIC32 families of microcontrollers and thedsPIC30 and dsPIC33 families of digital signal controllers.These compilers provide powerful integrationcapabilities, superior code optimization and ease ofuse.For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.25.3 HI-TECH C for Various DeviceFamiliesThe HI-TECH C Compiler code development systemsare complete ANSI C compilers for <strong>Microchip</strong>’s PIC<strong>family</strong> of microcontrollers and the dsPIC <strong>family</strong> of digitalsignal controllers. These compilers provide powerfulintegration capabilities, omniscient code generationand ease of use.For easy source level debugging, the compilers providesymbol information that is optimized to the MPLAB IDEdebugger.The compilers include a macro assembler, linker, preprocessor,and one-step driver, and can run on multipleplatforms.25.4 MPASM AssemblerThe MPASM Assembler is a full-featured, universalmacro assembler for PIC10/12/16/18 MCUs.The MPASM Assembler generates relocatable objectfiles for the MPLINK Object Linker, Intel ® standard HEXfiles, MAP files to detail memory usage and symbolreference, absolute LST files that contain source linesand generated machine code and COFF files fordebugging.The MPASM Assembler features include:• Integration into MPLAB IDE projects• User-defined macros to streamlineassembly code• Conditional assembly for multi-purposesource files• Directives that allow complete control over theassembly process25.5 MPLINK Object Linker/MPLIB Object LibrarianThe MPLINK Object Linker combines relocatableobjects created by the MPASM Assembler and theMPLAB C18 C Compiler. It can link relocatable objectsfrom precompiled libraries, using directives from alinker script.The MPLIB Object Librarian manages the creation andmodification of library files of precompiled code. Whena routine from a library is called from a source file, onlythe modules that contain that routine will be linked inwith the application. This allows large libraries to beused efficiently in many different applications.The object linker/library features include:• Efficient linking of single libraries instead of manysmaller files• Enhanced code maintainability by groupingrelated modules together• Flexible creation of libraries with easy modulelisting, replacement, deletion and extraction25.6 MPLAB Assembler, Linker andLibrarian for Various DeviceFamiliesMPLAB Assembler produces relocatable machinecode from symbolic assembly language for PIC24,PIC32 and dsPIC devices. MPLAB C Compiler usesthe assembler to produce its object file. The assemblergenerates relocatable object files that can then bearchived or linked with other relocatable object files andarchives to create an executable file. Notable featuresof the assembler include:• Support for the entire device instruction set• Support for fixed-point and floating-point data• Command line interface• Rich directive set• Flexible macro language• MPLAB IDE compatibilityDS39747E-page 208© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY25.7 MPLAB SIM Software SimulatorThe MPLAB SIM Software Simulator allows codedevelopment in a PC-hosted environment by simulatingthe PIC MCUs and dsPIC ® DSCs on an instructionlevel. On any given instruction, the data areas can beexamined or modified and stimuli can be applied froma comprehensive stimulus controller. Registers can belogged to files for further run-time analysis. The tracebuffer and logic analyzer display extend the power ofthe simulator to record and track program execution,actions on I/O, most peripherals and internal registers.The MPLAB SIM Software Simulator fully supportssymbolic debugging using the MPLAB C Compilers,and the MPASM and MPLAB Assemblers. The softwaresimulator offers the flexibility to develop anddebug code outside of the hardware laboratory environment,making it an excellent, economical softwaredevelopment tool.25.8 MPLAB REAL ICE In-CircuitEmulator SystemMPLAB REAL ICE In-Circuit Emulator System is<strong>Microchip</strong>’s next generation high-speed emulator for<strong>Microchip</strong> Flash DSC and MCU devices. It debugs andprograms PIC ® Flash MCUs and dsPIC ® Flash DSCswith the easy-to-use, powerful graphical user interface ofthe MPLAB Integrated Development Environment (IDE),included with each kit.The emulator is connected to the design engineer’s PCusing a high-speed USB 2.0 interface and is connectedto the target with either a connector compatible with incircuitdebugger systems (RJ11) or with the new highspeed,noise tolerant, Low-Voltage Differential Signal(LVDS) interconnection (CAT5).The emulator is field upgradable through future firmwaredownloads in MPLAB IDE. In upcoming releases ofMPLAB IDE, new devices will be supported, and newfeatures will be added. MPLAB REAL ICE offers significantadvantages over competitive emulators includinglow-cost, full-speed emulation, run-time variablewatches, trace analysis, complex breakpoints, a ruggedizedprobe interface and long (up to three meters) interconnectioncables.25.9 MPLAB ICD 3 In-Circuit DebuggerSystemMPLAB ICD 3 In-Circuit Debugger System is <strong>Microchip</strong>'smost cost effective high-speed hardwaredebugger/programmer for <strong>Microchip</strong> Flash Digital SignalController (DSC) and microcontroller (MCU)devices. It debugs and programs PIC ® Flash microcontrollersand dsPIC ® DSCs with the powerful, yet easyto-usegraphical user interface of MPLAB IntegratedDevelopment Environment (IDE).The MPLAB ICD 3 In-Circuit Debugger probe is connectedto the design engineer's PC using a high-speedUSB 2.0 interface and is connected to the target with aconnector compatible with the MPLAB ICD 2 or MPLABREAL ICE systems (RJ-11). MPLAB ICD 3 supports allMPLAB ICD 2 headers.25.10 PICkit 3 In-Circuit Debugger/Programmer andPICkit 3 Debug ExpressThe MPLAB PICkit 3 allows debugging and programmingof PIC ® and dsPIC ® Flash microcontrollers at amost affordable price point using the powerful graphicaluser interface of the MPLAB Integrated DevelopmentEnvironment (IDE). The MPLAB PICkit 3 is connectedto the design engineer's PC using a full speed USBinterface and can be connected to the target via an<strong>Microchip</strong> debug (RJ-11) connector (compatible withMPLAB ICD 3 and MPLAB REAL ICE). The connectoruses two device I/O pins and the reset line to implementin-circuit debugging and In-Circuit Serial Programming.The PICkit 3 Debug Express include the PICkit 3, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 209

PIC24FJ128GA010 FAMILY25.11 PICkit 2 DevelopmentProgrammer/Debugger andPICkit 2 Debug ExpressThe PICkit 2 Development Programmer/Debugger isa low-cost development tool with an easy to use interfacefor programming and debugging <strong>Microchip</strong>’s Flashfamilies of microcontrollers. The full featuredWindows ® programming interface supports baseline(PIC10F, PIC12F5xx, PIC16F5xx), midrange(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bitmicrocontrollers, and many <strong>Microchip</strong> Serial EEPROMproducts. With <strong>Microchip</strong>’s powerful MPLAB IntegratedDevelopment Environment (IDE) the PICkit 2enables in-circuit debugging on most PIC ® microcontrollers.In-Circuit-Debugging runs, halts and singlesteps the program while the PIC microcontroller isembedded in the application. When halted at a breakpoint,the file registers can be examined and modified.The PICkit 2 Debug Express include the PICkit 2, demoboard and microcontroller, hookup cables and CDROMwith user’s guide, lessons, tutorial, compiler andMPLAB IDE software.25.12 MPLAB PM3 Device ProgrammerThe MPLAB PM3 Device Programmer is a universal,CE compliant device programmer with programmablevoltage verification at VDDMIN and VDDMAX formaximum reliability. It features a large LCD display(128 x 64) for menus and error messages and a modular,detachable socket assembly to support variouspackage types. The ICSP cable assembly is includedas a standard item. In Stand-Alone mode, the MPLABPM3 Device Programmer can read, verify and programPIC devices without a PC connection. It can also setcode protection in this mode. The MPLAB PM3connects to the host PC via an RS-232 or USB cable.The MPLAB PM3 has high-speed communications andoptimized algorithms for quick programming of largememory devices and incorporates an MMC card for filestorage and data applications.25.13 Demonstration/DevelopmentBoards, Evaluation Kits, andStarter KitsA wide variety of demonstration, development andevaluation boards for various PIC MCUs and dsPICDSCs allows quick application development on fully functionalsystems. Most boards include prototyping areas foradding custom circuitry and provide application firmwareand source code for examination and modification.The boards support a variety of features, including LEDs,temperature sensors, switches, speakers, RS-232interfaces, LCD displays, potentiometers and additionalEEPROM memory.The demonstration and development boards can beused in teaching environments, for prototyping customcircuits and for learning about various microcontrollerapplications.In addition to the PICDEM and dsPICDEM demonstration/developmentboard series of circuits, <strong>Microchip</strong>has a line of evaluation kits and demonstration softwarefor analog filter design, KEELOQ ® security ICs, CAN,IrDA ® , PowerSmart battery management, SEEVAL ®evaluation system, Sigma-Delta ADC, flow ratesensing, plus many more.Also available are starter kits that contain everythingneeded to experience the specified device. This usuallyincludes a single application and debug capability, allon one board.Check the <strong>Microchip</strong> web page (www.microchip.com)for the complete list of demonstration, developmentand evaluation kits.DS39747E-page 210© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY26.0 ELECTRICAL CHARACTERISTICSThis section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will beprovided in future revisions of this document as it becomes available.Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditionsfor extended periods may affect device reliability. Functional operation of the device at these, or any other conditionsabove the parameters indicated in the operation listings of this specification, is not implied.Absolute Maximum Ratings (†)Ambient temperature under bias...............................................................................................................-40°C to +85°CStorage temperature .............................................................................................................................. -65°C to +150°CVoltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0VVoltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +6.0VVoltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8VMaximum current out of VSS pin ...........................................................................................................................300 mAMaximum current into VDD pin (Note 1)................................................................................................................250 mAMaximum output current sunk by any I/O pin..........................................................................................................25 mAMaximum output current sunk by any I/O pin..........................................................................................................25 mAMaximum output current sourced by any I/O pin ....................................................................................................25 mAMaximum current sunk by all ports .......................................................................................................................200 mAMaximum current sourced by all ports (Note 1)....................................................................................................200 mANote 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).FIGURE 26-1:FREQUENCY/VOLTAGE GRAPH3.00V2.75V2.50V2.75VVoltage VDDCORE (1)2.25V2.00V16 MHzFrequency32 MHzNote 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V.†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device reliability.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 211

PIC24FJ128GA010 FAMILY26.1 DC CharacteristicsTABLE 26-1:TABLE 26-2:VDD Range(in Volts)OPERATING MIPS vs. VOLTAGETemp Range(in °C)Max MIPSPIC24FJ128GA010 Family2.0-3.6V -40°C to +85°C 16THERMAL OPERATING CONDITIONSRating Symbol Min Typ Max UnitPIC24FJ128GA010 Family:Operating Junction Temperature Range TJ -40 — +125 °COperating Ambient Temperature Range TA -40 — +85 °CPower Dissipation:Internal Chip Power Dissipation:PINT = VDD x (IDD – Σ IOH) PD PINT + PI/O WI/O Pin Power Dissipation:PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA WTABLE 26-3:THERMAL PACKAGING CHARACTERISTICSCharacteristic Symbol Typ Max Unit NotesPackage Thermal Resistance, 14x14x1 mm TQFP θJA 50 — °C/W (Note 1)Package Thermal Resistance, 12x12x1 mm TQFP θJA 69.4 — °C/W (Note 1)Package Thermal Resistance, 10x10x1 mm TQFP θJA 76.6 — °C/W (Note 1)Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.1.5 — — VTABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONSDC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Symbol Characteristic Min Typ (1) Max Units ConditionsOperating VoltageDC10 Supply VoltageVDD 2.7 — 3.6 V Regulator enabledVDD VDDCORE — 3.6 V Regulator disabledVDDCORE 2.0 — 2.75 V Regulator disabledDC12 VDR RAM Data RetentionVoltage (2)DC16 VPOR VDD Start Voltageto ensure internalPower-on Reset signal— VSS — VDC17 SVDD VDD Rise Rateto ensure internalPower-on Reset signal0.05 — — V/ms 0-3.3V in 0.1s0-2.5V in 60 msNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.2: This is the limit to which VDD can be lowered without losing RAM data.DS39747E-page 212© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 26-5:DC CHARACTERISTICSDC CHARACTERISTICS: OPERATING CURRENT (IDD)Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParameterNo.Typical (1) Max Units ConditionsOperating Current (IDD) (2)DC20 1.6 4.0 mA -40°CDC20a 1.6 4.0 mA +25°CDC20b 1.6 4.0 mA +85°CDC20d 1.6 4.0 mA -40°CDC20e 1.6 4.0 mA +25°CDC20f 1.6 4.0 mA +85°CDC23 6.0 12 mA -40°CDC23a 6.0 12 mA +25°CDC23b 6.0 12 mA +85°CDC23d 6.0 12 mA -40°CDC23e 6.0 12 mA +25°CDC23f 6.0 12 mA +85°CDC24 20 32 mA -40°CDC24a 20 32 mA +25°CDC24b 20 32 mA +85°CDC24d 20 32 mA -40°CDC24e 20 32 mA +25°CDC24f 20 32 mA +85°CDC31 70 150 μA -40°C2.5V (3) 1 MIPS3.6V (4)2.5V (3) 4 MIPS3.6V (4)2.5V (3) 16 MIPS3.6V (4)2.5V (3) DC31a 100 200 μA +25°CDC31b 200 400 μA +85°CDC31d 70 150 μA -40°CLPRC (31 kHz)DC31e 100 200 μA +25°C3.6V (4)DC31f 200 400 μA +85°CNote 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidanceonly and are not tested.2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/Opin loading and switching rate, oscillator type, internal code execution pattern and temperature, also havean impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory areoperational. No peripheral modules are operating and PMD bits are set.3: On-chip voltage regulator disabled (ENVREG tied to VSS).4: On-chip voltage regulator enabled (ENVREG tied to VDD).© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 213

PIC24FJ128GA010 FAMILYTABLE 26-6:DC CHARACTERISTICSDC CHARACTERISTICS: IDLE CURRENT (IIDLE)Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParameterNo.Typical (1) Max Units ConditionsIdle Current (IIDLE): Core Off, Clock On Base Current (2)DC40 0.7 2 mA -40°CDC40a 0.7 2 mA +25°CDC40b 0.7 2 mA +85°CDC40d 0.7 2 mA -40°CDC40e 0.7 2 mA +25°CDC40f 0.7 2 mA +85°CDC43 2.1 4 mA -40°CDC43a 2.1 4 mA +25°CDC43b 2.1 4 mA +85°CDC43d 2.1 4 mA -40°CDC43e 2.1 4 mA +25°CDC43f 2.1 4 mA +85°CDC47 6.8 8 mA -40°CDC47a 6.8 8 mA +25°CDC47b 6.8 8 mA +85°CDC47c 6.8 8 mA -40°CDC47d 6.8 8 mA +25°CDC47e 6.8 8 mA +85°CDC51 150 500 μA -40°C2.5V (3) 1 MIPS3.6V (4)2.5V (3) 4 MIPS3.6V (4)2.5V (3) 16 MIPS3.6V (4)2.5V (3) DC51a 150 500 μA +25°CDC51b 150 500 μA +85°CDC51d 150 500 μA -40°CLPRC (31 kHz)DC51e 150 500 μA +25°C3.6V (4)DC51f 150 500 μA +85°CNote 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidanceonly and are not tested.2: Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off.3: On-chip voltage regulator disabled (ENVREG tied to VSS).4: On-chip voltage regulator enabled (ENVREG tied to VDD).DS39747E-page 214© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY2.0V (3)2.0V (3)TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)DC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParameterNo.Typical (1) Max Units ConditionsPower-Down Current (IPD) (2)DC60 3 25 μA -40°CDC60a 3 45 μA +25°CDC60b 100 600 μA +85°CDC60f 20 40 μA -40°CBase Power-Down Current (5)DC60g 27 60 μA +25°C 3.6V (4)DC60h 120 600 μA +85°CModule Differential CurrentDC61 10 25 μA -40°CDC61a 10 25 μA +25°CDC61b 10 25 μA +85°CDC61f 10 25 μA -40°CWatchdog Timer Current: ΔIWDT (5)DC61g 10 25 μA +25°C 3.6V (4)DC61h 10 25 μA +85°CDC62 8 15 μA -40°CDC62a 8 15 μA +25°C 2.0V (3)DC62b 8 15 μA +85°CRTCC + Timer1 w/32 kHz Crystal:DC62f 8 15 μA -40°CΔIRTCC (5)DC62g 8 15 μA +25°C 3.6V (4)DC62h 8 15 μA +85°CNote 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidanceonly and are not tested.2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs andpulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear.3: On-chip voltage regulator disabled (ENVREG tied to VSS).4: On-chip voltage regulator enabled (ENVREG tied to VDD).5: The Δ current is the additional current consumed when the module is enabled. This current should beadded to the base IPD current.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 215

PIC24FJ128GA010 FAMILYTABLE 26-8:DC CHARACTERISTICSParamNo.DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONSStandard Operating Conditions: 2.0V to 3.6V (unless otherwisestated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialSym Characteristic Min Typ (1) Max Units ConditionsVIL Input Low Voltage (4)DI10 I/O pins with ST buffer: VSS — 0.2 VDD VDI11 I/O pins with TTL buffer: VSS — 0.15 VDD VDI15 MCLR VSS — 0.2 VDD VDI16 OSC1 (XT mode) VSS — 0.2 VDD VDI17 OSC1 (HS mode) VSS — 0.2 VDD VDI18 I/O pins with I2C buffer: VSS — 0.3 VDD VDI19I/O pins with SMBusVSS — 0.8 V SMBus enabledbuffer:VIH Input High Voltage (4)DI20I/O pins with ST buffer:With Analog FunctionsDigital-Only0.8 VDD0.8 VDD——VDD5.5VVDI21I/O pins with TTL buffer:With Analog FunctionsDigital-Only0.25 VDD+ 0.80.25 VDD+ 0.8DI25 MCLR 0.8 VDD — VDD VDI26 OSC1 (XT mode) 0.7 VDD — VDD VDI27 OSC1 (HS mode) 0.7 VDD — VDD VDI28I/O pins with 12C buffer:With Analog FunctionsDigital-Only0.7 VDD0.7 VDD——VDD5.5VVDI29I/O pins with SMBUS buffer:With Analog FunctionsDigital-Only2.12.1——VDD5.5VDD5.5VVVV2.5V ≤ VPIN ≤ VDDDI30 ICNPU CNxx Pull-up Current 50 250 400 μA VDD = 3.3V, VPIN = VSSIIL Input Leakage Current (2,3)DI50 I/O Ports — — +1 μA VSS ≤ VPIN ≤ VDD,Pin at high-impedanceDI51 Analog Input pins — — +1 μA VSS ≤ VPIN ≤ VDD,Pin at high-impedanceDI55 MCLR — — +1 μA VSS ≤ VPIN ≤ VDDDI56 OSC1 — — +1 μA VSS ≤ VPIN ≤ VDD,XT and HS modesNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specifiedlevels represent normal operating conditions. Higher leakage current may be measured at different inputvoltages.3: Negative current is defined as current sourced by the pin.4: Refer to Table 1-2 for I/O pins buffer types.DS39747E-page 216© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 26-9:DC CHARACTERISTICSDC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Sym Characteristic Min Typ (1) Max Units ConditionsVOL Output Low VoltageDO10 I/O Ports — — 0.4 V IOL = 8.5 mA, VDD = 3.6V— — 0.4 V IOL = 6.0 mA, VDD = 2.0VDO16 OSC2/CLKO — — 0.4 V IOL = 8.5 mA, VDD = 3.6V— — 0.4 V IOL = 6.0 mA, VDD = 2.0VVOH Output High VoltageDO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V2.4 — — V IOH = -6.0 mA, VDD = 3.6V1.65 — — V IOH = -1.0 mA, VDD = 2.0V1.4 — — V IOH = -3.0 mA, VDD = 2.0VDO26 OSC2/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V1.4 — — V IOH = -3.0 mA, VDD = 2.0VNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.TABLE 26-10:DC CHARACTERISTICSDC CHARACTERISTICS: PROGRAM MEMORYStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Sym Characteristic Min Typ (1) Max Units ConditionsProgram Flash MemoryD130 EP Cell Endurance 100 1K — E/W -40°C to +85°CD131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operatingvoltageD132B VPEW VDD for Self-Timed Erase/ 2.25 — 3.6 VWriteD133A TIW Self-Timed Write Cycle — 3 — msTimeD134 TRETD Characteristic Retention 20 — — Year Provided no other specifications areviolatedD135 IDDP Supply Current during — 10 — mAProgrammingNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 217

PIC24FJ128GA010 FAMILYTABLE 26-11:INTERNAL VOLTAGE REGULATOR SPECIFICATIONSOperating Conditions: -40°C < TA < +85°C (unless otherwise stated)ParamNo.Symbol Characteristics Min Typ Max Units CommentsVRGOUT Regulator Output Voltage — 2.5 — VCEFCExternal Filter CapacitorValue4.7 10 — μF Series resistance < 3 Ohm recommended;< 5 Ohm required.TVREG — 10 — μs ENVREG = VDDTPWRT — 64 — ms ENVREG = VSSDS39747E-page 218© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY26.2 AC Characteristics and Timing ParametersThe information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters.TABLE 26-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – ACStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)AC CHARACTERISTICSOperating temperature -40°C ≤ TA ≤ +85°C for IndustrialOperating voltage VDD range as described in Section 26.1 “DC Characteristics”.FIGURE 26-2:LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONSLoad Condition 1 – for all pins except OSC2Load Condition 2 – for OSC2VDD/2RLPinCLVSSPinVSSCLRLCL= 464Ω= 50 pF for all pins except OSC215 pF for OSC2 outputTABLE 26-13:CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINSParamNo.Symbol Characteristic Min Typ (1) Max Units ConditionsDO50 COSC2 OSC2/CLKO pin — — 15 pF In XT and HS modes whenexternal clock is used to driveOSC1.DO56 CIO All I/O pins and OSC2 — — 50 pF EC modeDO58 CB SCLx, SDAx — — 400 pF In I 2 C modeNote 1:Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 219

PIC24FJ128GA010 FAMILYFIGURE 26-3:EXTERNAL CLOCK TIMINGQ4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3OSC1OS25OS20OS30OS30OS31OS31CLKOOS40OS41TABLE 26-14:AC CHARACTERISTICSEXTERNAL CLOCK TIMING REQUIREMENTSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Sym Characteristic Min Typ (1) Max Units ConditionsOS10 FOSC External CLKI Frequency(External clocks allowedonly in EC mode)DC3Oscillator Frequency 3.53.51031——————3281083233MHzMHzMHzMHzMHzkHzECECPLLXTXTPLLHSSOSCOS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10for FOSC valueOS25 TCY Instruction Cycle Time (2) 62.5 — DC nsOS30OS31TosL,TosHTosR,TosFExternal Clock in (OSC1)High or Low TimeExternal Clock in (OSC1)Rise or Fall Time0.45 x TOSC — — ns EC— — 20 ns ECOS40 TckR CLKO Rise Time (3) — 6 10 nsOS41 TckF CLKO Fall Time (3) — 6 10 nsNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified valuesare based on characterization data for that particular oscillator type under standard operating conditionswith the device executing code. Exceeding these specified limits may result in an unstable oscillatoroperation and/or higher than expected current consumption. All devices are tested to operate at “Min.”values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the“Max.” cycle time limit is “DC” (no clock) for all devices.3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for theQ1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).DS39747E-page 220© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 26-15:AC CHARACTERISTICSPLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Sym Characteristic (1) Min Typ (2) Max Units Conditions3 — 8 MHz ECPLL, HSPLL, XTPLLOS50 FPLLI PLL Input FrequencyRange (2) modesOS51 FSYS On-Chip VCO System 8 — 32 MHzFrequencyOS52 TLOCK PLL Start-up Time— — 2 ms(Lock Time)OS53 DCLK CLKO Stability (Jitter) -2 1 +2 %Note 1: These parameters are characterized but not tested in manufacturing.2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.TABLE 26-16:AC CHARACTERISTICSAC CHARACTERISTICS: INTERNAL RC ACCURACYStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Characteristic Min Typ Max Units ConditionsInternal FRC Accuracy @ 8 MHz (1)F20 FRC -2 — +2 % +25°C V dd = 3.0 - 3.6V-5 — +5 % -40°C ≤ TA ≤ +85°C V dd = 3.0 - 3.6VLegend: TBD = To Be DeterminedNote 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.TABLE 26-17:AC CHARACTERISTICSINTERNAL RC ACCURACYStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Characteristic Min Typ Max Units ConditionsLPRC @ 31 kHz (1)F21 -15 — +15 % -40°C ≤ TA ≤ +85°C VDD = 3.0 - 3.6VNote 1: Change of LPRC frequency as VDD changes.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 221

PIC24FJ128GA010 FAMILYFIGURE 26-4:CLKO AND I/O TIMING CHARACTERISTICSI/O Pin(Input)DI35DI40I/O Pin(Output)Old ValueDO31DO32New ValueNote: Refer to Figure 26-2 for load conditions.TABLE 26-18: CLKO AND I/O TIMING REQUIREMENTSAC CHARACTERISTICSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialParamNo.Sym Characteristic Min Typ (1) Max Units ConditionsDO31 TIOR Port Output Rise Time — 10 25 nsDO32 TIOF Port Output Fall Time — 10 25 nsDI35 TINP INTx pin High or Low 20 — — nsTime (output)DI40 TRBP CNx High or Low Time(input)2 — — TCYNote 1:Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.DS39747E-page 222© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTABLE 26-19:ADC MODULE SPECIFICATIONSAC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V(unless otherwise stated)Operating temperature -40°C ≤ TA ≤ +85°CParamNo.Symbol Characteristic Min. Typ Max. Units ConditionsAD01 AVDD Module VDD Supply Greater ofVDD – 0.3or 2.0Device Supply— Lesser ofVDD + 0.3or 3.6AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 VReference InputsAD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD VAD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 VAD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 VVoltageAnalog InputAD10 VINH-VINL Full-Scale Input Span VREFL VREFH V See Note 2AD11 VIN Absolute Input Voltage AVSS – 0.3 AVDD + 0.3 VAD12 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL = 0V,AVDD = VREFH = 5V,Source Impedance = 2.5 kΩAD13 — Leakage Current — ±0.001 ±0.610 μA VINL = AVSS = VREFL = 0V,AVDD = VREFH = 3V,Source Impedance = 2.5 kΩAD14 VINL Absolute VINL Input Voltage AVSS – 0.3 AVDD/2 VAD17 RIN Recommended— — 2.5KImpedance of Analog VoltageADC AccuracyAD20a Nr Resolution 10 data bits bitsAD21a INL Integral Nonlinearity (2) — +1

PIC24FJ128GA010 FAMILYTABLE 26-20: ADC CONVERSION TIMING REQUIREMENTS (1)AC CHARACTERISTICSParamNo.Standard Operating Conditions: 2.0V to 3.6V (unlessotherwise stated)Operating temperature -40°C ≤ TA ≤ +85°C for IndustrialSym Characteristic Min Typ (1) Max Units ConditionsAD50 TAD ADC Clock Period 75 — — ns TCY = 75ns, ADxCON3in default stateAD51 tRC ADC Internal RC Oscillator — 250 — nsPeriodConversion RateAD55 tCONV Conversion Time — 12 — TADAD56 FCNV Throughput Rate — — 500 kspsAD57 tSAMP Sample Time — 1 — TADClock ParametersAD61 tPSS Sample Start Delay from 2 — 3 TADSetting Sample bit (SAMP)Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance,especially at elevated temperatures.DS39747E-page 224© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY27.0 PACKAGING INFORMATION27.1 Package Marking Information64-Lead TQFP (10x10x1 mm)ExampleXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNNPIC24FJ128GA006-I/PT e3071001780-Lead TQFP (12x12x1 mm)ExampleXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNNPIC24FJ128GA008-I/PT e30710017100-Lead TQFP (12x12x1 mm)ExampleXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNNPIC24FJ128GA010-I/PT e30710017100-Lead TQFP (14x14x1 mm)ExampleXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNNPIC24FJ128GA010-I/PF e30710017Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability codePb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( e3 )can be found on the outer packaging for this package.Note: In the event the full <strong>Microchip</strong> part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 225

PIC24FJ128GA010 FAMILY27.2 Package DetailsThe following sections give the technical details of the packages.64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]Note:For the most current package drawings, please see the <strong>Microchip</strong> Packaging Specification located athttp://www.microchip.com/packagingDD1eE1EbNNOTE 1 123 NOTE 2cφAαA2βLA1L1UnitsMILLIMETERSDimension Limits MIN NOM MAXNumber of Leads N 64Lead Pitch e 0.50 BSCOverall Height A – – 1.20Molded Package Thickness A2 0.95 1.00 1.05Standoff A1 0.05 – 0.15Foot Length L 0.45 0.60 0.75Footprint L1 1.00 REFFoot Angle φ 0° 3.5° 7°Overall Width E 12.00 BSCOverall Length D 12.00 BSCMolded Package Width E1 10.00 BSCMolded Package Length D1 10.00 BSCLead Thickness c 0.09 – 0.20Lead Width b 0.17 0.22 0.27Mold Draft Angle Top α 11° 12° 13°Mold Draft Angle Bottom β 11° 12° 13°Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. Chamfers at corners are optional; size may vary.3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.4. Dimensioning and tolerancing per ASME Y14.5M.BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.<strong>Microchip</strong> Technology Drawing C04-085BDS39747E-page 226© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]Note:For the most current package drawings, please see the <strong>Microchip</strong> Packaging Specification located athttp://www.microchip.com/packagingDD1eE1EbNNOTE 1c123 NOTE 2AαβφLA1L1A2UnitsMILLIMETERSDimension Limits MIN NOM MAXNumber of Leads N 80Lead Pitch e 0.50 BSCOverall Height A – – 1.20Molded Package Thickness A2 0.95 1.00 1.05Standoff A1 0.05 – 0.15Foot Length L 0.45 0.60 0.75Footprint L1 1.00 REFFoot Angle φ 0° 3.5° 7°Overall Width E 14.00 BSCOverall Length D 14.00 BSCMolded Package Width E1 12.00 BSCMolded Package Length D1 12.00 BSCLead Thickness c 0.09 – 0.20Lead Width b 0.17 0.22 0.27Mold Draft Angle Top α 11° 12° 13°Mold Draft Angle Bottom β 11° 12° 13°Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. Chamfers at corners are optional; size may vary.3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.4. Dimensioning and tolerancing per ASME Y14.5M.BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.<strong>Microchip</strong> Technology Drawing C04-092B© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 227

PIC24FJ128GA010 FAMILY100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP]Note:For the most current package drawings, please see the <strong>Microchip</strong> Packaging Specification located athttp://www.microchip.com/packagingDD1eEE1bN123NOTE 1 NOTE 2αcAβφLA1L1A2UnitsMILLIMETERSDimension Limits MIN NOM MAXNumber of Leads N 100Lead Pitch e 0.40 BSCOverall Height A – – 1.20Molded Package Thickness A2 0.95 1.00 1.05Standoff A1 0.05 – 0.15Foot Length L 0.45 0.60 0.75Footprint L1 1.00 REFFoot Angle φ 0° 3.5° 7°Overall Width E 14.00 BSCOverall Length D 14.00 BSCMolded Package Width E1 12.00 BSCMolded Package Length D1 12.00 BSCLead Thickness c 0.09 – 0.20Lead Width b 0.13 0.18 0.23Mold Draft Angle Top α 11° 12° 13°Mold Draft Angle Bottom β 11° 12° 13°Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. Chamfers at corners are optional; size may vary.3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.4. Dimensioning and tolerancing per ASME Y14.5M.BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.<strong>Microchip</strong> Technology Drawing C04-100BDS39747E-page 228© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILY100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP]Note:For the most current package drawings, please see the <strong>Microchip</strong> Packaging Specification located athttp://www.microchip.com/packagingDD1eE1EbNNOTE 1 123NOTE 2AαcβφLA1L1A2UnitsMILLIMETERSDimension Limits MIN NOM MAXNumber of Leads N 100Lead Pitch e 0.50 BSCOverall Height A – – 1.20Molded Package Thickness A2 0.95 1.00 1.05Standoff A1 0.05 – 0.15Foot Length L 0.45 0.60 0.75Footprint L1 1.00 REFFoot Angle φ 0° 3.5° 7°Overall Width E 16.00 BSCOverall Length D 16.00 BSCMolded Package Width E1 14.00 BSCMolded Package Length D1 14.00 BSCLead Thickness c 0.09 – 0.20Lead Width b 0.17 0.22 0.27Mold Draft Angle Top α 11° 12° 13°Mold Draft Angle Bottom β 11° 12° 13°Notes:1. Pin 1 visual index feature may vary, but must be located within the hatched area.2. Chamfers at corners are optional; size may vary.3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.4. Dimensioning and tolerancing per ASME Y14.5M.BSC: Basic Dimension. Theoretically exact value shown without tolerances.REF: Reference Dimension, usually without tolerance, for information purposes only.<strong>Microchip</strong> Technology Drawing C04-110B© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 229

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 230© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYAPPENDIX A:REVISION HISTORYRevision A (September 2005)Original data sheet for PIC24FJ128GA010 <strong>family</strong>devices.Revision B (March 2006)Update of electrical specifications.Revision C (June 2006)Update of electrical specifications.Revision D (September 2007)Minor changes in the overall data sheetRevision E (October 2009)Updated to remove Preliminary status.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 231

PIC24FJ128GA010 FAMILYNOTES:DS39747E-page 232© 2009 <strong>Microchip</strong> Technology Inc.

INDEXAACCharacteristics .......................................................... 219Internal RC Accuracy ........................................ 221Load Conditions ........................................................ 219Temperature and Voltage Specifications .................. 219Alternate Interrupt Vector Table (AIVT)............................... 59Arithmetic Logic Unit (ALU).................................................26AssemblerMPASM Assembler...................................................208BBaud Rate Error Calculation (BRGH = 0) ......................... 140Block Diagrams10-Bit High-Speed A/D Converter............................. 17416-Bit Timer1 Module................................................ 1058-Bit Multiplexed Address and Data Application ....... 156Accessing Program Memory with Table Instructions .. 44Addressable Parallel Slave Port ............................... 154Comparator I/O Operating Modes............................. 183Comparator Voltage Reference ................................ 187Connections for On-Chip Voltage Regulator............. 195Device Clock ............................................................... 93I 2 C............................................................................. 132Input Capture ............................................................ 113LCD Control .............................................................. 156Legacy Parallel Slave Port........................................ 154Master Mode, Demultiplexed Addressing ................. 154Master Mode, Fully Multiplexed Addressing ............. 155Master Mode, Partially Multiplexed Addressing ........ 155Multiplexed Addressing Application ..........................155Output Compare Module........................................... 115Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data)...156Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data).....156Partially Multiplexed Addressing Application ............ 155PIC24F CPU Core ...................................................... 22PIC24FJ128GA010 Family (General) ......................... 12PMP Module ............................................................. 147Program Space Visibility Operation ............................45Reset System.............................................................. 53RTCC ........................................................................157Shared Port Structure ...............................................103SPI Master, Frame Master Connection..................... 129SPI Master, Frame Slave Connection....................... 129SPI Master/Slave Connection (Enhanced Buffer Modes)128SPI Master/Slave Connection (Standard Mode) ....... 128SPI Slave, Frame Master Connection....................... 129SPI Slave, Frame Slave Connection......................... 129SPIx Module (Enhanced Mode) ................................ 123SPIx Module (Standard Mode).................................. 122Timer2 and Timer4 (16-Bit Synchronous)................. 109Timer2/3 and Timer4/5 (32-Bit)................................. 108Timer3 and Timer5 (16-Bit Asynchronous) ............... 109UART ........................................................................139Watchdog Timer (WDT) ............................................ 196Brown-out Reset (BOR)and On-Chip Voltage Regulator................................ 195CC CompilersMPLAB C18.............................................................. 208Clock Switchingand Clock Frequency................................................ 101Enabling...................................................................... 99Operation.................................................................... 99Oscillator Sequence.................................................... 99Code ExamplesBasic Code Sequence for Clock Switching............... 100Erasing a Program Memory Block.............................. 50Initiating a Programming Sequence............................ 51Loading Write Buffers ................................................. 51Port Write/Read ........................................................ 104Programming a Single Word of Flash Program Memory52PWRSAV Instruction Syntax..................................... 101Comparator Module .......................................................... 183Comparator Voltage Reference ........................................ 187Configuring ............................................................... 187Configuration Bits ............................................................. 189Configuration Register Protection..................................... 197Configuring Analog Port Pins............................................ 104Core Features....................................................................... 916-Bit Architecture ........................................................ 9Easy Migration............................................................ 10Oscillator Options, Features ......................................... 9Power-Saving Technology............................................ 9CPU .................................................................................... 21Control Registers........................................................ 24Programmer’s Model .................................................. 23CPU Clocking Scheme ....................................................... 94CRCExample Setup ......................................................... 169Operation in Power Save Modes.............................. 171Overview................................................................... 169Registers .................................................................. 169User Interface ........................................................... 170Customer Change Notification Service............................. 237Customer Notification Service .......................................... 237Customer Support............................................................. 237DData MemoryAddress Space ........................................................... 29Width .................................................................. 29Memory Map for PIC24F128GA010 Family Devices.. 29Near Data Space ........................................................ 30Organization and Alignment ....................................... 30SFR Space ................................................................. 30Software Stack ........................................................... 42DC Characteristics............................................................ 212I/O Pin Input Specifications....................................... 216I/O Pin Output Specifications.................................... 217Idle Current (IIDLE) .................................................... 214Operating Current (IDD) ............................................ 213Operating MIPS vs. Voltage ..................................... 212Power-Down Current (IPD)........................................ 215Program Memory...................................................... 217Temperature and Voltage Specifications.................. 212Thermal Operating Conditions.................................. 212Thermal Packaging Characteristics.......................... 212Development Support ....................................................... 207DS39747E-page 233© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYEElectrical Characteristics...................................................211Absolute Maximum Ratings ...................................... 211ENVREG pin ..................................................................... 195EquationsA/D Conversion Clock Period ................................... 180Calculating the PWM Period ..................................... 117Calculation for Maximum PWM Resolution............... 117Relationship Between Device and SPI Clock Speed ................................................................................ 130UART Baud Rate with BRGH = 0 ............................. 140UART Baud Rate with BRGH = 1 ............................. 140Errata .................................................................................... 8FFlash Configuration Words.......................................... 28, 189Flash Program Memory....................................................... 47Control Registers ........................................................ 48Enhanced ICSP .......................................................... 48Operations .................................................................. 48Programming Algorithm .............................................. 50RTSP Operation.......................................................... 48Table Instructions........................................................ 47FSCMand Device Resets...................................................... 57Delay for Crystal and PLL Clock Sources................... 57II/O Ports ............................................................................ 103Parallel I/O (PIO)....................................................... 103Write/Read Timing .................................................... 104I 2 CClock Rates............................................................... 133Communicating as Master in aSingle Master Environment............................... 131Setting Baud Rate When Operating as Bus Master.. 133Slave Address Masking ............................................ 133Implemented Interrupt Vectors (table)................................. 61In-Circuit Debugger ........................................................... 197In-Circuit Serial Programming (ICSP) ............................... 197Input Capture .................................................................... 113Registers................................................................... 114Input Change Notification.................................................. 104Instruction SetOverview ................................................................... 201Summary................................................................... 199Inter-Integrated Circuit (I 2 C).............................................. 131Internal RC OscillatorUse with WDT ........................................................... 196Internet Address................................................................ 237Interrupt Control and Status Registers................................ 62IECx ............................................................................ 62IFSx............................................................................. 62INTCON1, INTCON2 .................................................. 62IPCx ............................................................................ 62Interrupt Controller .............................................................. 59Interrupt Setup Procedures ................................................. 91Initialization ................................................................. 91Interrupt Disable.......................................................... 91Interrupt Service Routine (ISR)................................... 91Trap Service Routine (TSR)........................................ 91Interrupt Vector Table (IVT) ................................................ 59Interrupts Coincident with Power Save Instructions.......... 102MMemory Organization ......................................................... 27<strong>Microchip</strong> Internet Web Site.............................................. 237Mode of Operation ............................................................ 115MPLAB ASM30 Assembler, Linker, Librarian ................... 208MPLAB Integrated Development Environment Software.. 207MPLAB PM3 Device Programmer .................................... 210MPLAB REAL ICE In-Circuit Emulator System ................ 209MPLINK Object Linker/MPLIB Object Librarian ................ 208OOpen-Drain Configuration................................................. 104Oscillator Configuration ...................................................... 93Clock Switching Mode Configuration Bits ................... 94Control Registers........................................................ 95CLKDIV............................................................... 95OSCCON............................................................ 95OSCTUN ............................................................ 95Output Compare ............................................................... 115PPackaging ......................................................................... 225Details....................................................................... 226Marking..................................................................... 225Pad Configuratiuon Map ..................................................... 39Parallel Master Port (PMP) ............................................... 147POR and Long Oscillator Start-up Times ........................... 57Power-on Reset (POR)and On-Chip Voltage Regulator................................ 195Power-Saving Features .................................................... 101Power-Saving ModesDoze ......................................................................... 102Instruction-Based...................................................... 101Idle.................................................................... 102Sleep ................................................................ 101Program Address Space..................................................... 27Memory Map for PIC24FJ128GA010 Family Devices 27Program and Data Memory SpacesInterfacing................................................................... 42Program MemoryData Access Using Table Instructions........................ 44Hard Memory Vectors................................................. 28Interrupt Vector........................................................... 28Organization ............................................................... 28Reading Data Using Program Space Visibility............ 45Reset Vector............................................................... 28Table InstructionsTBLRDH ............................................................. 44TBLRDL.............................................................. 44Program SpaceAddress Construction ................................................. 43Addressing.................................................................. 42Data Access From, Address Generation .................... 43Program Verification and Code Protection ....................... 197Programmer’s Model .......................................................... 21Pulse-Width Modulation Mode.......................................... 117Duty Cycle ................................................................ 117Period ....................................................................... 117DS39747E-page 234© 2009 <strong>Microchip</strong> Technology Inc.

RReader Response ............................................................. 238Register MapADC ............................................................................ 37CPU Core.................................................................... 31CRC ............................................................................ 41Dual Comparator......................................................... 40I2C1 ............................................................................ 35I2C2 ............................................................................ 35ICN.............................................................................. 33Input Capture .............................................................. 34Interrupt Controller ...................................................... 32NVM ............................................................................ 41Output Compare ......................................................... 34Parallel Master/Slave Port .......................................... 40PMD ............................................................................ 41PORTA........................................................................37PORTB........................................................................38PORTC ....................................................................... 38PORTD ....................................................................... 38PORTE........................................................................39PORTF........................................................................39PORTG ....................................................................... 39Real-Time Clock and Calendar................................... 40SPI1 ............................................................................ 36SPI2 ............................................................................ 36System ........................................................................41Timer........................................................................... 33UART1 ........................................................................36UART2 ........................................................................36RegistersAD1CHS (A/D Input Select) ...................................... 178AD1CON1 (A/D Control 1) ........................................ 175AD1CON2 (A/D Control 2) ........................................ 176AD1CON3 (A/D Control 3) ........................................ 177AD1CSSL (A/D Input Scan Select) ........................... 179AD1PCFG (A/D Port Configuration)..........................179ALCFGRPT (Alarm Configuration)............................161ALMINSEC (Alarm Minutes and Seconds Value) ..... 165ALMTHDY (Alarm Month and Day Value) ................ 164ALWDHR (Alarm Weekday and Hours Value).......... 164CLKDIV (Clock Divider) .............................................. 97CMCON (Comparator Control) ................................. 184CORCON (Core Control) ...................................... 25, 63CRCCON (CRC Control) .......................................... 171CVRCON (Comparator Voltage Reference Control). 188DEVID (Device ID) .................................................... 193DEVREV (Device Revision) ...................................... 194Flash Configuration Word 1 ...................................... 190Flash Configuration Word 2 ...................................... 192I2CxCON (I2Cx Control) ........................................... 134I2CxMSK (I2Cx Slave Mode Address Mask) ............ 138I2CxSTAT (I2Cx Status) ........................................... 136ICxCON (Input Capture x Control) ............................ 114IEC0 (Interrupt Enable Control 0) ............................... 71IEC1 (Interrupt Enable Control 1) ............................... 72IEC2 (Interrupt Enable Control 2) ............................... 73IEC3 (Interrupt Enable Control 3) ............................... 74IEC4 (Interrupt Enable Control 4) ............................... 75IFS0 (Interrupt Flag Status 0) ..................................... 66IFS1 (Interrupt Flag Status 1) ..................................... 67IFS2 (Interrupt Flag Status 2) ..................................... 68IFS3 (Interrupt Flag Status 3) ..................................... 69IFS4 (Interrupt Flag Status 4) ..................................... 70INTCON1 (Interrupt Control 1).................................... 64INTCON2 (Interrupt Control 2).................................... 65IPC0 (Interrupt Priority Control 0) ............................... 76IPC1 (Interrupt Priority Control 1) ............................... 77IPC10 (Interrupt Priority Control 10) ........................... 86IPC11 (Interrupt Priority Control 11) ........................... 86IPC12 (Interrupt Priority Control 12) ........................... 87IPC13 (Interrupt Priority Control 13) ........................... 88IPC15 (Interrupt Priority Control 15) ........................... 89IPC16 (Interrupt Priority Control 16) ........................... 90IPC2 (Interrupt Priority Control 2) ............................... 78IPC3 (Interrupt Priority Control 3) ............................... 79IPC4 (Interrupt Priority Control 4) ............................... 80IPC5 (Interrupt Priority Control 5) ............................... 81IPC6 (Interrupt Priority Control 6) ............................... 82IPC7 (Interrupt Priority Control 7) ............................... 83IPC8 (Interrupt Priority Control 8) ............................... 84IPC9 (Interrupt Priority Control 9) ............................... 85MINSEC (Minutes and Seconds Value).................... 163MTHDY (Month and Day Value)............................... 162NVMCON (Flash Memory Control)............................. 49OCxCON Output Compare x Control) ...................... 119OSCCON (Oscillator Control)..................................... 95OSCTUN (FRC Oscillator Tune)................................. 98PMADDR (Parallel Port Address)............................. 151PMAEN (Parallel Port Enable).................................. 151PMCON (Parallel Port Control)................................. 148PMMODE (Parallel Port Mode)................................. 150PMSTAT (Parallel Port Status)................................. 152RCFGCAL (RTCC Calibration and Configuration).... 159RCON (Reset Control)................................................ 54SPIxCON1 (SPIx Control 1)...................................... 126SPIxCON2 (SPIx Control 2)...................................... 127SPIxSTAT (SPIx Status and Control) ....................... 124SR (CPU STATUS)............................................... 24, 63T1CON (Timer1 Control) .......................................... 106TxCON (Timer2/4 Control)........................................ 110TyCON (Timer3/5 Control)........................................ 111UxMODE (UARTx Mode).......................................... 142UxSTA (UARTx Status and Control)......................... 144WKDYHR (Weekday and Hours Value).................... 163YEAR (Year Value)................................................... 162Reset Sequence ................................................................. 59Resets................................................................................. 53Clock Source Selection............................................... 55Device Times.............................................................. 55Revision History................................................................ 231RTCCAlarm ........................................................................ 166Configuring ....................................................... 166Interrupt ............................................................ 166ALRMVAL Register Mappings.................................. 164Calibration ................................................................ 166Control Registers...................................................... 159Module Registers...................................................... 158Mapping............................................................ 158RTCVAL Register Mapping ...................................... 162DS39747E-page 235© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYSSelective Peripheral Module Control................................. 102Serial Peripheral Interface (SPI) ....................................... 121Setup for Continuous Output Pulse Generation................ 116Setup for Single Output Pulse Generation ........................ 115Software Simulator (MPLAB SIM)..................................... 209Software Stack Pointer, Frame PointerCALL Stack Frame...................................................... 42Special Features ............................................................... 189Code Protection ........................................................ 189Flexible Configuration ...............................................189In-Circuit Emulation...................................................189In-Circuit Serial Programming (ICSP) ....................... 189JTAG Boundary Scan Interface ................................ 189Watchdog Timer (WDT) ............................................ 189Special Function Register Reset States..............................57Symbols Used in Opcode Descriptions............................. 200TTimer1 Module .................................................................. 105Timer2/3 Module ............................................................... 107Timer4/5 Module ............................................................... 107Timing DiagramsCLKO and I/O ........................................................... 222External Clock........................................................... 220Timing RequirementsCapacitive Loading on Output Pin ............................ 219CLKO and I/O ........................................................... 222External Clock........................................................... 220Timing SpecificationsPLL Clock.................................................................. 221UUARTBaud Rate Generator (BRG) .................................... 140Infrared Support........................................................ 141IrDABuilt-in Encoder and Decoder........................... 141External Support, Clock Output ........................ 141Operation of UxCTS and UxRTS Control Pins ......... 141Receiving8-Bit or 9-Bit Data Mode ................................... 141Transmitting8-Bit Data Mode................................................ 1419-Bit Data Mode................................................ 141Break and Sync Sequence ............................... 141Universal Asynchronous Receiver Transmitter (UART) ... 139VVDDCORE/VCAP Pin ........................................................... 195Voltage Regulator (On-Chip) ............................................ 195WWatchdog Timer (WDT).................................................... 196Control Register........................................................ 196Programming Considerations ................................... 196WWW Address ................................................................. 237WWW, On-Line Support ....................................................... 8DS39747E-page 236© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYTHE MICROCHIP WEB SITE<strong>Microchip</strong> provides online support via our WWW site atwww.microchip.com. This web site is used as a meansto make files and information easily available tocustomers. Accessible by using your favorite Internetbrowser, the web site contains the followinginformation:• Product Support – Data sheets and errata,application notes and sample programs, designresources, user’s guides and hardware supportdocuments, latest software releases and archivedsoftware• General Technical Support – Frequently AskedQuestions (FAQ), technical support requests,online discussion groups, <strong>Microchip</strong> consultantprogram member listing• Business of <strong>Microchip</strong> – Product selector andordering guides, latest <strong>Microchip</strong> press releases,listing of seminars and events, listings of<strong>Microchip</strong> sales offices, distributors and factoryrepresentativesCUSTOMER SUPPORTUsers of <strong>Microchip</strong> products can receive assistancethrough several channels:• Distributor or Representative• Local Sales Office• Field Application Engineer (FAE)• Technical Support• Development Systems Information LineCustomers should contact their distributor,representative or field application engineer (FAE) forsupport. Local sales offices are also available to helpcustomers. A listing of sales offices and locations isincluded in the back of this document.Technical support is available through the web siteat: http://support.microchip.comCUSTOMER CHANGE NOTIFICATIONSERVICE<strong>Microchip</strong>’s customer notification service helps keepcustomers current on <strong>Microchip</strong> products. Subscriberswill receive e-mail notification whenever there arechanges, updates, revisions or errata related to aspecified product <strong>family</strong> or development tool of interest.To register, access the <strong>Microchip</strong> web site atwww.microchip.com, click on Customer ChangeNotification and follow the registration instructions.© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 237

PIC24FJ128GA010 FAMILYREADER RESPONSEIt is our intention to provide you with the best documentation possible to ensure successful use of your <strong>Microchip</strong> product.If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentationcan better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.Please list the following information, and use this outline to provide us with your comments about this document.To:RE:Technical Publications ManagerReader ResponseTotal Pages Sent ________From: NameCompanyAddressCity / State / ZIP / CountryTelephone: (_______) _________ - _________Application (optional):Would you like a reply? Y NFAX: (______) _________ - _________Device:PIC24FJ128GA010 FamilyLiterature Number:DS39747EQuestions:1. What are the best features of this document?2. How does this document meet your hardware and software development needs?3. Do you find the organization of this document easy to follow? If not, why?4. What additions to the document do you think would enhance the structure and subject?5. What deletions from the document could be made without affecting the overall usefulness?6. Is there any incorrect or misleading information (what and where)?7. How would you improve this document?DS39747E-page 238© 2009 <strong>Microchip</strong> Technology Inc.

PIC24FJ128GA010 FAMILYPRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.PIC 24 FJ 128 GA0 10 T - I / PT - XXX<strong>Microchip</strong> TrademarkArchitectureFlash Memory FamilyProgram Memory Size (KB)Product GroupPin CountTape and Reel Flag (if applicable)Temperature RangePackagePatternExamples:a) PIC24FJ128GA008-I/PT 301:General purpose PIC24F, 96 KB programmemory, 80-pin, Industrial temp.,TQFP package, QTP pattern #301.b) PIC24FJ128GA010-I/PT:General purpose PIC24F, 128 KB programmemory, 100-pin, Industrial temp.,TQFP package.Architecture 24 = 16-bit modified Harvard without DSPFlash Memory Family FJ = Flash program memoryProduct GroupGA0 = General purpose microcontrollersPin Count 06 = 64-pin08 = 80-pin10 = 100-pinTemperature Range I = -40°C to +85°C (Industrial)Package PT = 64-Lead, 80-Lead, 100-Lead (12x12x1 mm)TQFP (Thin Quad Flatpack)PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)PatternThree-digit QTP, SQTP, Code or Special Requirements(blank otherwise)ES = Engineering Sample© 2009 <strong>Microchip</strong> Technology Inc. DS39747E-page 239

WORLDWIDE SALES AND SERVICEAMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://support.microchip.comWeb Address:www.microchip.comAtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075ClevelandIndependence, OHTel: 216-447-0464Fax: 216-447-0643DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitFarmington Hills, MITel: 248-538-2250Fax: 248-538-2260KokomoKokomo, INTel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Santa ClaraSanta Clara, CATel: 408-961-6444Fax: 408-961-6445TorontoMississauga, Ontario,CanadaTel: 905-673-0699Fax: 905-673-6509ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - Hong Kong SARTel: 852-2401-1200Fax: 852-2401-3431China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660Fax: 86-755-8203-1760China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XiamenTel: 86-592-2388138Fax: 86-592-2388130China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256China - ZhuhaiTel: 86-756-3210040Fax: 86-756-3210049ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444Fax: 91-80-3090-4080India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166Fax: 81-45-471-6122Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or82-2-558-5934Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-6578-300Fax: 886-3-6578-370Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-582003/26/09DS39747E-page 240© 2009 <strong>Microchip</strong> Technology Inc.

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