TMS320C5X USER'S GUIDE

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TablesTables1–1 Characteristics of the ’C5x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162–1 Number of Serial/Parallel Ports Available in Different ’C5x Package Types . . . . . . . . . . . . 292–2 IEEE Std.1149.1 (JTAG)/Boundary-Scan Interface Configurations for the ’C5x . . . . . . . 2123–1 ’C5x CPU Internal Hardware Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343–2 Auxiliary Register Arithmetic Unit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3194–1 Address Loading Into the Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434–2 Circular Buffer Control Register (CBCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474–3 Processor Mode Status Register (PMST) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484–4 On-Chip RAM Configuration Using OVLY and RAM Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 4104–5 Status Register 0 (ST0) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4114–6 Status Register 1 (ST1) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4134–7 Product Shifter Mode as Determined by PM Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4164–8 Conditions for Branch, Call, and Return Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4174–9 Groups for Multiconditional Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4194–10 Multi-cycle Instructions Transformed Into Single-Cycle Instructions by theRepeat Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4234–11 Repeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4244–12 Instructions Not Meaningful to Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4274–13 Nonrepeatable Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4294–14 Interrupt Vector Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4374–15 CPU Registers’ Bit Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4464–16 Peripheral Registers’ Bit Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4475–1 Indirect Addressing Opcode Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575–2 Indirect Addressing Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595–3 Instruction Field Bit Values for Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595–4 Bit-Reversed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5135–5 Instructions That Support Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5146–1 Instruction Set Opcode Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626–2 Instruction Set Descriptions Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 646–3 Instruction Set Descriptions Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666–4 Accumulator Memory Reference Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696–5 Auxiliary Registers and Data Memory Page Pointer Instructions . . . . . . . . . . . . . . . . . . . . 6136–6 Parallel Logic Unit (PLU) Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6146–7 TREG0, PREG, and Multiply Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6156–8 Branch and Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6176–9 I/O and Data Memory Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619xxviii
Tables6–10 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6206–11 Address Blocks for On-Chip Single-Access RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6267–1 Pipeline Operation of 1-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737–2 Pipeline Operation of 2-Word Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757–3 Pipeline Operation with Branch Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777–4 Pipeline Operation with Branch Not Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797–5 Pipeline Operation with Subroutine Call and Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7117–6 Pipeline Operation with ARx Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7157–7 Pipeline Operation with ARx Load and NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 7177–8 Pipeline Operation with ARx Load and NOP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 7197–9 Pipeline Operation with External Bus Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7217–10 Latencies Required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7248–1 ’C50 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888–2 ’C51 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898–3 ’C52 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898–4 ’C53 and ’C53S Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8108–5 ’LC56 and ’LC57 Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8108–6 ’C57S Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8118–7 ’C5x Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8128–8 ’C50 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8168–9 ’C51 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8168–10 ’C52 Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8168–11 ’C53 and ’C53S Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8168–12 ’LC56, ’LC57, and ’C57S Local Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . 8178–13 Data Page 0 Address Map — CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8188–14 Global Data Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8218–15 Address Ranges for On-Chip Single-Access RAM During External DMA . . . . . . . . . . . . 8258–16 Number of CLKOUT1 Cycles Per Access for Various Numbers of Wait States . . . . . . . . 8429–1 Data Page 0 Address Map — Peripheral Registers and I/O Ports . . . . . . . . . . . . . . . . . . . . 929–2 Standard Clock Options (’C50, ’C51, ’C52, ’C53, and ’C53S only) . . . . . . . . . . . . . . . . . . . 979–3 PLL Clock Options (’LC56, ’C57S, and ’LC57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989–4 Timer Control Register (TCR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9109–5 Program/Data Wait-State Register (PDWSR) Address Ranges(’C50, ’C51, and ’C52 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9149–6 Program/Data Wait-State Register (PDWSR) Address Ranges(’C53S, ’LC56, and ’C57 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9149–7 Number of CLKOUT1 Cycles per Access for Various Numbers of Wait States . . . . . . . . 9159–8 I/O Port Wait-State Register (IOWSR) Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . 9169–9 Wait-State Control Register (CWSR) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9179–10 Wait-State Field Values and Number of Wait States as a Function ofCWSR Bits 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9189–11 Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9249–12 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9269–13 Serial Port Control Register (SPC) Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928Contentsxxix
Page 2 and 3: IMPORTANT NOTICETexas Instruments (
Page 4 and 5: Notational How to UseConventionsThi
Page 6 and 7: Information About Cautions and Warn
Page 8 and 9: Technical Related Documentation Art
Page 10 and 11: Technical Articles17) Lovrich, A.,
Page 12 and 13: Technical Articles8) Rabiner, L.R.,
Page 14 and 15: Technical Articles6) Lovrich, A. an
Page 16 and 17: If You Need AssistanceIf You Need A
Page 18: Contents3 Central Processing Unit (
Page 21 and 22: Contents8.6.2 External DMA . . . .
Page 23 and 24: ContentsC.2.2 Pipeline . . . . . .
Page 25 and 26: FiguresFigures1-1 Evolution of the
Page 27: Figures9-31 SP/BSP Transmitter Func
Page 31 and 32: TablesC-3 TMS320C2x-to-TMS320C5x Ac
Page 33 and 34: Examples8-2 Moving External Data to
Page 35 and 36: Chapter 1IntroductionThis user’s
Page 37 and 38: TMS320 Family OverviewFigure 1-1. E
Page 39 and 40: TMS320C5x Overview1.2 TMS320C5x Ove
Page 41 and 42: TMS320C5x Key Features1.3 TMS320C5x
Page 43 and 44: TMS320C5x Key Features On-chip peri
Page 45 and 46: Chapter 2Architectural OverviewThis
Page 47 and 48: Bus Structure2.1 Bus StructureSepar
Page 49 and 50: Central Processing Unit (CPU)2.2.3
Page 51 and 52: On-Chip Memoryblock B0 can be confi
Page 53 and 54: On-Chip Peripherals2.4.4 Parallel I
Page 55 and 56: Test/Emulation2.5 Test/EmulationOn
Page 57 and 58: Chapter 3Central Processing Unit (C
Page 59 and 60: Functional OverviewFigure 3-1. Bloc
Page 61 and 62: Functional OverviewTable 3-1. ’C5
Page 63 and 64: Central Arithmetic Logic Unit (CALU
Page 71 and 72: Parallel Logic Unit (PLU)3.3 Parall
Page 73 and 74: Auxiliary Register Arithmetic Unit
Page 75 and 76: Auxiliary Register Arithmetic Unit
Page 77 and 78: Summary of Registers3.5 Summary of
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Summary of Registers3.5.8 Global Me
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Summary of Registers3.5.18 Status R
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Chapter 4Program ControlProgram con
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Program Counter (PC)Table 4-1. Addr
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Program-Memory Address Generation4.
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Status and Control RegistersFigure
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Status and Control RegistersTable 4
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Status and Control RegistersFigure
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CNF ÁÁStatus and Control Register
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Status and Control RegistersTable 4
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Conditional Operations4.5 Condition
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Conditional OperationsYou can combi
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Conditional OperationsThe condition
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Single Instruction Repeat FunctionT
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Block Repeat Function4.7 Block Repe
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Block Repeat Functionprocessor will
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Block Repeat FunctionExample 4-12.
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---ÁÁÁÁÁ--- ÁÁÁÁÁ---ÁÁ
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Interrupts4.8.3 Interrupt Flag Regi
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Interrupts4.8.6 Nonmaskable Interru
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InterruptsExample 4-13. Modifying R
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Reset4.9 ResetReset (RS) is a nonma
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ResetTable 4-16.Peripheral Register
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ResetFigure 4-10. RS and HOLD Inter
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Power-Down Mode4.10.3 Power Down Us
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Chapter 5Addressing ModesThis chapt
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Direct AddressingNote:The DP is not
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Indirect Addressing5.2.1 Indirect A
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Indirect Addressing*0- Decrement by
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Indirect AddressingTable 5-2. Indir
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1 1 0 0 ÁÁ ÁÁÁÁ ÁÁ1 ÁÁ0
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Indirect AddressingExample 5-10. Se
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Immediate Addressing5.3.2 Long Imme
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Dedicated-Register Addressing5.4 De
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Memory-Mapped Register Addressing5.
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Circular Addressing5.6 Circular Add
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Chapter 6Assembly Language Instruct
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Instruction Set Symbols and Notatio
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Instruction Set Summaryextra cycle
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Instruction Set SummaryTable 6-4. A
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Instruction Set SummaryTable 6-5. A
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Instruction Set SummaryTable 6-7. T
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Instruction Set SummaryTable 6-7. T
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Instruction Set SummaryTable 6-8. B
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Instruction Set SummaryTable 6-10.C
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Instruction Set Descriptions6.3 Ins
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Execution(PC) + 1 → PC(ACC) + (dm
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Table 6-11 lists the on-chip single
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SyntaxOperandsABSNoneOpcode 15 14 1
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SyntaxOperandsADCBNoneOpcode 15 14
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Short immediate addressing:(PC) + 1
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Example 2 ADD *+,0,AR0Before Instru
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Syntax Direct: ADDC dmaIndirect: AD
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Syntax Direct: ADDS dmaIndirect: AD
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Syntax Direct: ADDT dmaIndirect: AD
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Syntax ADRK #kOperands 0 ≤ k ≤
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WordsCycles1 (Direct or indirect ad
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SyntaxOperandsANDBNoneOpcode 15 14
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Syntax Direct: APL [#lk,] dmaIndire
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Example 1 APL #0023h,DAT96 ;(DP = 0
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SyntaxOperandsBACCNoneOpcode 15 14
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Syntax BANZ pma [, {ind} [,ARn ]]Op
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Syntax BANZD pma [, {ind} [,ARn ]]O
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Syntax BCND pma, cond [,cond1] [,..
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Syntax BCNDD pma, cond [,cond1] [,.
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Syntax BD pma [, {ind} [,ARn ]]Oper
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Words 1CyclesCycles for a Single In
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Words 1You can maintain software co
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Indirect addressing with DEST speci
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Cycles for a Repeat (RPT) Execution
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Example 1 BLDD #300h,20h ;(DP = 6)B
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Syntax General syntax: BLPD src, ds
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OperandSource: SARAMDestination: Ex
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OperandSource: ExternalDestination:
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SyntaxBSAR shiftOperands 1 ≤ shif
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SyntaxOperandsCALADNoneOpcode 15 14
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SyntaxCALLD pma [,{ind} [,ARn]]Oper
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Syntax CC pma cond [,cond1] [,...]O
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Syntax CCD pma cond [,cond1] [,...]
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SyntaxOperandsCLRC control bitcontr
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SyntaxOperandsCMPLNoneOpcode 15 14
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CyclesCycles for a Single Instructi
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DescriptionIf a long immediate cons
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SyntaxOperandsCRGTNoneOpcode 15 14
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SyntaxOperandsCRLTNoneOpcode 15 14
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Syntax Direct: DMOV dmaIndirect: DM
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SyntaxOperandsEXARNoneOpcode 15 14
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SyntaxOperandsIDLE2NoneOpcode 15 14
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The reserved interrupt vectors can
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Syntax Direct: LACC dma [,shift]Ind
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Example 1 LACC DAT6,4 ;(DP = 8, SXM
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CyclesFor the short immediate addre
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Syntax Direct: LACT dmaIndirect: LA
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Syntax Direct: LAMM dmaIndirect: LA
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Syntax Direct: LAR ARx, dmaIndirect
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Cycles for a Single Instruction (sh
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CyclesFor the short immediate addre
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Syntax Direct: LMMR dma, #addrIndir
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Example 1Example 2LMMR DBMR,#300hBe
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Example 1 LPH DAT0 ;(DP = 4)Before
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Syntax Direct: LT dmaIndirect: LT {
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Syntax Direct: LTA dmaIndirect: LTA
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Syntax Direct: LTD dmaIndirect: LTD
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Example 2 LTD *,AR3 ;(TRM = 0)Befor
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Words 2contents of the dma are mult
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Example 1 MAC 0FF00h,02h ;(DP = 6,
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DescriptionThe contents of the prod
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Syntax Direct: MADD dmaIndirect: MA
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Operand1: DARAM/ROM2: External1: SA
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Syntax Direct: MADS dmaIndirect: MA
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Syntax Direct: MAR dmaIndirect: MAR
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Syntax Direct: MPY dmaIndirect:MPY
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Example 1 MPY DAT13 ;(DP = 8)Before
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Example 2 NEG ;(OVM = 0)Before Inst
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SyntaxOperandsNOPNoneOpcode 15 14 1
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The NORM instruction executes the a
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Syntax Direct: OPL [#lk], dmaIndire
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Example 1Example 2Example 3Example
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DescriptionIf a long immediate cons
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SyntaxOperandsORBNoneOpcode 15 14 1
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SyntaxOperandsPOPNoneOpcode 15 14 1
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Syntax Direct: POPD dmaIndirect: PO
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Syntax Direct: PSHD dmaIndirect: PS
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SyntaxOperandsPUSHNoneOpcode 15 14
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SyntaxOperandsRETNoneOpcode 15 14 1
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ExampleRETC GEQ,NOV ;A return, RET,
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Example RETCD C ;A return, RET, is
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SyntaxOperandsRETENoneOpcode 15 14
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SyntaxOperandsROLNoneOpcode 15 14 1
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SyntaxOperandsRORNoneOpcode 15 14 1
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Syntax Direct: RPT dmaIndirect:RPT
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Example 3Example 4RPT #1 ;Repeat ne
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CyclesThe RPTB instruction is not r
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SyntaxOperandsSACBNoneOpcode 15 14
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Example 1 SACH DAT10,1 ;(DP = 4)Bef
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Example 1 SACL DAT11,1 ;(DP = 4)Bef
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Example 1 SAMM PRD ;(DP = 6)Before
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Example 2 SATH ;(SXM = 1)Before Ins
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SyntaxOperandsSBBNoneOpcode 15 14 1
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Syntax SBRK #kOperands 0 ≤ k ≤
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An IDLE instruction must not follow
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SyntaxOperandsSFLBNoneOpcode 15 14
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Example 1 SFR ;(SXM = 0)Before Inst
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SyntaxOperandsSPACNoneOpcode 15 14
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Example 1 SPH DAT3 ;(DP = 4, PM = 0
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Example 1 SPL DAT5 ;(DP = 1, PM = 2
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SyntaxSPM constantOperands 0 ≤ co
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Short immediate addressing:(PC) + 1
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Example 2 SUB *-,1,AR0 ;(SXM = 0)Be
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Syntax Direct: TBLW dmaIndirect: TB
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OperandSource: SARAMDestination: SA
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Syntax XC n ,cond [,cond1] [,...]Op
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Syntax Direct: XOR dmaIndirect:XOR
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Example 1 XOR DAT127 ;(DP = 511)Bef
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Syntax Direct: XPL [#lk,] dmaIndire
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Example 1 XPL #100h,DAT60 ;(DP = 0)
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Example 1 ZALR DAT3 ;(DP = 32)Befor
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SyntaxOperandsZPRNoneOpcode 15 14 1
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Pipeline Structure7.1 Pipeline Stru
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Pipeline OperationAssume memory loc
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Pipeline OperationCycle 5: F) Fetch
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Pipeline OperationR) Dummy operatio
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Pipeline OperationCycle 16: F)Fetch
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Pipeline Latency7.3 Pipeline Latenc
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7-26
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Memory Space Overview8.1 Memory Spa
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Memory Space OverviewFigure 8-1.
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Memory Space OverviewFigure 8-5.
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0 ÁÁÁÁÁ1 ÁÁÁÁÁProgram Mem
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Program MemoryTable 8-4. ’C53 and
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ÁÁÁÁÁ2ÁÁÁÁÁÁÁ2ÁÁÁÁ
Page 487 and 488:
Program MemoryInstruction addresses
Page 489 and 490:
Local Data MemoryTable 8-8. ’C50
Page 491 and 492:
Local Data Memory The 32-word scrat
Page 493 and 494:
Global Data Memory8.4 Global Data M
Page 495 and 496:
Input/Output (I/O) Space8.5 Input/O
Page 497 and 498:
Direct Memory Access (DMA)8.6.2 Ext
Page 499 and 500:
Memory Management8.7 Memory Managem
Page 501 and 502:
Memory Management8.7.2.2 Moving Dat
Page 503 and 504:
Memory ManagementExample 8-4. Movin
Page 505 and 506:
Boot Loader8.8 Boot LoaderSeveral o
Page 507 and 508:
Boot LoaderAn alternative to the HP
Page 509 and 510:
Boot Loader8.8.3.2 8-Bit Word Paral
Page 511 and 512:
Boot Loaderother means (for example
Page 513 and 514:
External Parallel Interface Operati
Page 515 and 516:
Software Wait-State Generation8.10
Page 517 and 518:
ÁÁÁ3233 ÁÁÁ3637 ÁÁÁÁÁÁ4
Page 519 and 520:
ÁÁÁ9293 ÁÁÁ94 ÁÁÁPeriphera
Page 521 and 522:
Peripheral Control9.1.3 Peripheral
Page 523 and 524:
Clock Generator9.2.2 PLL Clock Opti
Page 525 and 526:
5 ÁÁTRB ÁÁTimerFigure 9-3. Time
Page 527 and 528:
TimerExample 9-1. Code Initializati
Page 529 and 530:
Software-Programmable Wait-State Ge
Page 531 and 532:
Page 533 and 534:
Page 535 and 536:
General-Purpose I/O Pins9.5 General
Page 537 and 538:
Parallel I/O Ports9.6 Parallel I/O
Page 539 and 540:
Serial Port Interface9.7.1 Serial P
Page 541 and 542:
Serial Port InterfaceTable 9-12.Ser
Page 543 and 544:
ÁÁÁÁÁÁÁÁÁÁ14 13 12 9 Free
Page 545 and 546:
Serial Port InterfaceTable 9-13.Ser
Page 547 and 548:
Serial Port InterfaceDLB BitFigure
Page 549 and 550:
Serial Port InterfaceXRST and RRST
Page 551 and 552:
Serial Port InterfaceWhen XSREMPTY
Page 553 and 554:
Serial Port InterfaceFigure 9-16. B
Page 555 and 556:
Serial Port InterfaceFigure 9-18. B
Page 557 and 558:
Serial Port InterfaceUnlike transmi
Page 559 and 560:
Serial Port InterfaceAs shown in Fi
Page 561 and 562:
Serial Port InterfaceFigure 9-26. C
Page 563 and 564:
Serial Port InterfaceTransmitter ex
Page 565 and 566:
Serial Port InterfaceAnother cause
Page 567 and 568:
Serial Port InterfaceExample 9-4 sh
Page 569 and 570:
Buffered Serial Port (BSP) Interfac
Page 571 and 572:
Page 573 and 574:
Page 575 and 576:
Page 577 and 578:
Page 579 and 580:
Page 581 and 582:
Page 583 and 584:
Page 585 and 586:
Page 587 and 588:
Page 589 and 590:
Time-Division Multiplexed (TDM) Ser
Page 591 and 592:
Page 593 and 594:
X2 ÁÁXRDY RRDY ÁÁ ÁÁÁS2 ÁÁ
Page 595 and 596:
Page 597 and 598:
Page 599 and 600:
Page 601 and 602:
Page 603 and 604:
Host Port InterfaceThe HPI provides
Page 605 and 606:
Host Port InterfaceTable 9-24 summa
Page 607 and 608:
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Page 609 and 610:
Host Port InterfaceTable 9-26.HPI I
Page 611 and 612:
HINT ÁÁÁ0 ÁÁÁÁÁÁ11 ÁÁÁ1
Page 613 and 614:
Host Port InterfaceFigure 9-52. HPI
Page 615 and 616:
Internal HPI RAM read complete ÁÁ
Page 617 and 618:
Host Port InterfaceHost Port Interf
Page 619 and 620:
Comes out of reset ÁÁÁÁHost Por
Page 621 and 622:
100-Pin QFP Pinout (’C52)A.1 100-
Page 623 and 624:
100-Pin TQFP Pinout (’C51, ’C52
Page 625 and 626:
128-Pin TQFP Pinout (’LC57)A.3 12
Page 627 and 628:
132-Pin BQFP Pinout (’C50, ’C51
Page 629 and 630:
144-Pin TQFP Pinout (’C57S)A.5 14
Page 631 and 632:
100-Pin TQFP Device-Specific Pinout
Page 633 and 634:
Signal DescriptionsTable A-8. Memor
Page 635 and 636:
Signal DescriptionsTable A-10.Initi
Page 637 and 638:
Signal DescriptionsTable A-13.Oscil
Page 639 and 640:
Signal DescriptionsTable A-15.Seria
Page 641 and 642:
Signal DescriptionsTable A-17.Host
Page 643 and 644:
Signal DescriptionsTable A-18.Emula
Page 645 and 646:
Cycle Class-to-Instruction Set Summ
Page 647 and 648:
Cycle Class-to-Instruction Set Summ
Page 649 and 650:
Instruction Set-to-Cycle Class Summ
Page 651 and 652:
Page 653 and 654:
Page 655 and 656:
Page 657 and 658:
Package and Pin LayoutC.1 Package a
Page 659 and 660:
Package and Pin LayoutWhen a ’C25
Page 661 and 662:
Package and Pin LayoutThe ’C5x MP
Page 663 and 664:
TimingThe ’C5x has two additional
Page 665 and 666:
On-Chip Peripheral InterfacingC.3 O
Page 667 and 668:
’C2x-to-’C5x Instruction SetC.4
Page 669 and 670:
’C2x-to-’C5x Instruction SetTab
Page 671 and 672:
Page 673 and 674:
Page 675 and 676:
Appendix DADesign Considerations fo
Page 677 and 678:
Bus ProtocolD.2 Bus ProtocolThe IEE
Page 679 and 680:
Emulator Cable PodFigure D-2. Emula
Page 681 and 682:
Target System Test ClockD.5 Target
Page 683 and 684:
Connections Between the Emulator an
Page 685 and 686:
Emulation Timing CalculationsD.8 Em
Page 687 and 688:
Emulation Timing CalculationsCase 4
Page 689 and 690:
Appendix EAMemories, Sockets, and C
Page 691 and 692:
CrystalsE.3 CrystalsThis section li
Page 693 and 694:
Appendix FASubmitting ROM Codes to
Page 695 and 696:
TMS320 Development FlowF.2 TMS320 D
Page 697 and 698:
Appendix GADevelopment Support and
Page 699 and 700:
Development SupportG.1.3Technical T
Page 701 and 702:
Part Order InformationG.2.2Device N
Page 703 and 704:
Part Order InformationTable G-1. TM
Page 705 and 706:
Hewlett-Packard E2442A Preprocessor
Page 707 and 708:
Appendix HAGlossaryAA0-A15:ABU:ACC:
Page 709 and 710:
Glossaryautobuffering unit (ABU): A
Page 711 and 712:
GlossaryBSP address transmit regist
Page 713 and 714:
Glossarycircular buffer 1 start reg
Page 715 and 716:
Glossarydata receive shift register
Page 717 and 718:
GlossaryFFT:FIG:FO:See fast Fourier
Page 719 and 720:
Glossaryhost port interface (HPI):
Page 721 and 722:
Glossaryinterrupt mode (INTM) bit:
Page 723 and 724:
GlossaryOoff-chip:on-chip:A device
Page 725 and 726:
Glossaryprogram/data wait-state reg
Page 727 and 728:
Glossaryserial port control registe
Page 729 and 730:
GlossaryTDM data (TDAT): A single,
Page 731 and 732:
Glossarytimer prescaler counter (PS
Page 733 and 734:
GlossaryXXF:XH:XINT:See external fl
Page 735 and 736:
Summary of Updates in This Document
Page 737 and 738:
Page 739 and 740:
Page 741 and 742:
Page 743 and 744:
Page 745 and 746:
Page 747 and 748:
Page 749 and 750:
Page 751 and 752:
Page 753 and 754:
Page 755 and 756:
Index’C2x instruction compatibili
Page 757 and 758:
BCNDD instructiondescription 6-61ex
Page 759 and 760:
circular buffer 2 auxiliary registe
Page 761 and 762:
frame synchronization mode (FSM) bi
Page 763 and 764:
internal hardware summary 3-2 to 3-
Page 765 and 766:
MP/MC bit 4-9, 8-7, H-16MP/MC pin 8
Page 767 and 768:
product register (PREG) 3-7, 3-24,
Page 769 and 770:
SSACB instructiondescription 6-221s
Page 771 and 772:
status register 1 (ST1) (continued)
Page 773 and 774:
TMS320C5x (continued)compatibility
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TMS320C5X USER'S GUIDE

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