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TMS320C5X USER'S GUIDE
TMS320C5X USER'S GUIDE
TMS320C5X USER'S GUIDE
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TMS320 Family OverviewFigure 1–1. Evolution of the TMS320 FamilyIntroduction1-3
TMS320 Family Overview1.1 TMS320 Family OverviewThe TMS320 family consists of two types of single-chip DSPs: 16-bit fixedpointand 32-bit floating-point. These DSPs possess the operational flexibilityof high-speed controllers and the numerical capability of array processors.Combining these two qualities, the TMS320 processors are inexpensive alternativesto custom-fabricated VLSI and multichip bit-slice processors. Refer tosubsection 1.1.2, TMS320 Typical Applications, for a detailed list of applicationsof the TMS320 family. The following characteristics make this family theideal choice for a wide range of processing applications: Very flexible instruction set Inherent operational flexibility High-speed performance Innovative, parallel architectural design Cost-effectiveness1.1.1 History, Development, and Advantages of TMS320 DSPsIn 1982, Texas Instruments introduced the TMS32010 — the first fixed-pointDSP in the TMS320 family. Before the end of the year, the Electronic Productsmagazine awarded the TMS32010 the title “Product of the Year”. TheTMS32010 became the model for future TMS320 generations.Today, the TMS320 family consists of eight generations: the ’C1x, ’C2x, ’C2xx,’C5x, and ’C54x are fixed-point, the ’C3x and ’C4x are floating-point, and the’C8x is a multiprocessor. Figure 1–1 illustrates the performance gains that theTMS320 family has made over time with successive generations. Source codeis upward compatible from one fixed-point generation to the next fixed-pointgeneration (except for the ’C54x), and from one floating-point generation to thenext floating-point generation. Upward compatibility preserves the softwaregeneration of your investment, thereby providing a convenient and cost-efficientmeans to a higher-performance, more versatile DSP system.Each generation of TMS320 devices has a CPU and a variety of on-chipmemory and peripheral configurations for developing spin-off devices. Thesespin-off devices satisfy a wide range of needs in the worldwide electronicsmarket. When memory and peripherals are integrated into one processor, theoverall system cost is greatly reduced, and circuit board space is saved.1-2
TMS320 Family OverviewFigure 1–1. Evolution of the TMS320 FamilyIntroduction1-3
- Page 2 and 3: IMPORTANT NOTICETexas Instruments (
- Page 4 and 5: Notational How to UseConventionsThi
- Page 6 and 7: Information About Cautions and Warn
- Page 8 and 9: Technical Related Documentation Art
- Page 10 and 11: Technical Articles17) Lovrich, A.,
- Page 12 and 13: Technical Articles8) Rabiner, L.R.,
- Page 14 and 15: Technical Articles6) Lovrich, A. an
- Page 16 and 17: If You Need AssistanceIf You Need A
- Page 18: Contents3 Central Processing Unit (
- Page 21 and 22: Contents8.6.2 External DMA . . . .
- Page 23 and 24: ContentsC.2.2 Pipeline . . . . . .
- Page 25 and 26: FiguresFigures1-1 Evolution of the
- Page 27 and 28: Figures9-31 SP/BSP Transmitter Func
- Page 29 and 30: Tables6-10 Control Instructions . .
- Page 31 and 32: TablesC-3 TMS320C2x-to-TMS320C5x Ac
- Page 33 and 34: Examples8-2 Moving External Data to
- Page 35: Chapter 1IntroductionThis user’s
- Page 39 and 40: TMS320C5x Overview1.2 TMS320C5x Ove
- Page 41 and 42: TMS320C5x Key Features1.3 TMS320C5x
- Page 43 and 44: TMS320C5x Key Features On-chip peri
- Page 45 and 46: Chapter 2Architectural OverviewThis
- Page 47 and 48: Bus Structure2.1 Bus StructureSepar
- Page 49 and 50: Central Processing Unit (CPU)2.2.3
- Page 51 and 52: On-Chip Memoryblock B0 can be confi
- Page 53 and 54: On-Chip Peripherals2.4.4 Parallel I
- Page 55 and 56: Test/Emulation2.5 Test/EmulationOn
- Page 57 and 58: Chapter 3Central Processing Unit (C
- Page 59 and 60: Functional OverviewFigure 3-1. Bloc
- Page 61 and 62: Functional OverviewTable 3-1. ’C5
- Page 63 and 64: Central Arithmetic Logic Unit (CALU
- Page 65 and 66: Central Arithmetic Logic Unit (CALU
- Page 67 and 68: Central Arithmetic Logic Unit (CALU
- Page 69 and 70: Central Arithmetic Logic Unit (CALU
- Page 71 and 72: Parallel Logic Unit (PLU)3.3 Parall
- Page 73 and 74: Auxiliary Register Arithmetic Unit
- Page 75 and 76: Auxiliary Register Arithmetic Unit
- Page 77 and 78: Summary of Registers3.5 Summary of
- Page 79 and 80: Summary of Registers3.5.8 Global Me
- Page 81 and 82: Summary of Registers3.5.18 Status R
- Page 83 and 84: Chapter 4Program ControlProgram con
- Page 85 and 86: Program Counter (PC)Table 4-1. Addr
- Page 87 and 88:
Program-Memory Address Generation4.
- Page 89 and 90:
Status and Control RegistersFigure
- Page 91 and 92:
Status and Control RegistersTable 4
- Page 93 and 94:
Status and Control RegistersFigure
- Page 95 and 96:
CNF ÁÁStatus and Control Register
- Page 97 and 98:
Status and Control RegistersTable 4
- Page 99 and 100:
Conditional Operations4.5 Condition
- Page 101 and 102:
Conditional OperationsYou can combi
- Page 103 and 104:
Conditional OperationsThe condition
- Page 105 and 106:
Single Instruction Repeat FunctionT
- Page 107 and 108:
Single Instruction Repeat FunctionT
- Page 109 and 110:
Single Instruction Repeat FunctionT
- Page 111 and 112:
Single Instruction Repeat FunctionT
- Page 113 and 114:
Block Repeat Function4.7 Block Repe
- Page 115 and 116:
Block Repeat Functionprocessor will
- Page 117 and 118:
Block Repeat FunctionExample 4-12.
- Page 119 and 120:
---ÁÁÁÁÁ--- ÁÁÁÁÁ---ÁÁ
- Page 121 and 122:
Interrupts4.8.3 Interrupt Flag Regi
- Page 123 and 124:
Interrupts4.8.6 Nonmaskable Interru
- Page 125 and 126:
InterruptsExample 4-13. Modifying R
- Page 127 and 128:
Reset4.9 ResetReset (RS) is a nonma
- Page 129 and 130:
ResetTable 4-16.Peripheral Register
- Page 131 and 132:
ResetFigure 4-10. RS and HOLD Inter
- Page 133 and 134:
Power-Down Mode4.10.3 Power Down Us
- Page 135 and 136:
Chapter 5Addressing ModesThis chapt
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Direct AddressingNote:The DP is not
- Page 139 and 140:
Indirect Addressing5.2.1 Indirect A
- Page 141 and 142:
Indirect Addressing*0- Decrement by
- Page 143 and 144:
Indirect AddressingTable 5-2. Indir
- Page 145 and 146:
1 1 0 0 ÁÁ ÁÁÁÁ ÁÁ1 ÁÁ0
- Page 147 and 148:
Indirect AddressingExample 5-10. Se
- Page 149 and 150:
Immediate Addressing5.3.2 Long Imme
- Page 151 and 152:
Dedicated-Register Addressing5.4 De
- Page 153 and 154:
Memory-Mapped Register Addressing5.
- Page 155 and 156:
Circular Addressing5.6 Circular Add
- Page 157 and 158:
Chapter 6Assembly Language Instruct
- Page 159 and 160:
Instruction Set Symbols and Notatio
- Page 161 and 162:
Instruction Set Symbols and Notatio
- Page 163 and 164:
Instruction Set Symbols and Notatio
- Page 165 and 166:
Instruction Set Summaryextra cycle
- Page 167 and 168:
Instruction Set SummaryTable 6-4. A
- Page 169 and 170:
Instruction Set SummaryTable 6-5. A
- Page 171 and 172:
Instruction Set SummaryTable 6-7. T
- Page 173 and 174:
Instruction Set SummaryTable 6-7. T
- Page 175 and 176:
Instruction Set SummaryTable 6-8. B
- Page 177 and 178:
Instruction Set SummaryTable 6-10.C
- Page 179 and 180:
Instruction Set Descriptions6.3 Ins
- Page 181 and 182:
Execution(PC) + 1 → PC(ACC) + (dm
- Page 183 and 184:
Table 6-11 lists the on-chip single
- Page 185 and 186:
SyntaxOperandsABSNoneOpcode 15 14 1
- Page 187 and 188:
SyntaxOperandsADCBNoneOpcode 15 14
- Page 189 and 190:
Short immediate addressing:(PC) + 1
- Page 191 and 192:
Example 2 ADD *+,0,AR0Before Instru
- Page 193 and 194:
Syntax Direct: ADDC dmaIndirect: AD
- Page 195 and 196:
Syntax Direct: ADDS dmaIndirect: AD
- Page 197 and 198:
Syntax Direct: ADDT dmaIndirect: AD
- Page 199 and 200:
Syntax ADRK #kOperands 0 ≤ k ≤
- Page 201 and 202:
WordsCycles1 (Direct or indirect ad
- Page 203 and 204:
SyntaxOperandsANDBNoneOpcode 15 14
- Page 205 and 206:
Syntax Direct: APL [#lk,] dmaIndire
- Page 207 and 208:
Example 1 APL #0023h,DAT96 ;(DP = 0
- Page 209 and 210:
SyntaxOperandsBACCNoneOpcode 15 14
- Page 211 and 212:
Syntax BANZ pma [, {ind} [,ARn ]]Op
- Page 213 and 214:
Syntax BANZD pma [, {ind} [,ARn ]]O
- Page 215 and 216:
Syntax BCND pma, cond [,cond1] [,..
- Page 217 and 218:
Syntax BCNDD pma, cond [,cond1] [,.
- Page 219 and 220:
Syntax BD pma [, {ind} [,ARn ]]Oper
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Words 1CyclesCycles for a Single In
- Page 223 and 224:
Words 1You can maintain software co
- Page 225 and 226:
Indirect addressing with DEST speci
- Page 227 and 228:
Cycles for a Repeat (RPT) Execution
- Page 229 and 230:
Example 1 BLDD #300h,20h ;(DP = 6)B
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Words 1CyclesCycles for a Single In
- Page 233 and 234:
Syntax General syntax: BLPD src, ds
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OperandSource: SARAMDestination: Ex
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OperandSource: ExternalDestination:
- Page 239 and 240:
SyntaxBSAR shiftOperands 1 ≤ shif
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SyntaxOperandsCALADNoneOpcode 15 14
- Page 243 and 244:
SyntaxCALLD pma [,{ind} [,ARn]]Oper
- Page 245 and 246:
Syntax CC pma cond [,cond1] [,...]O
- Page 247 and 248:
Syntax CCD pma cond [,cond1] [,...]
- Page 249 and 250:
SyntaxOperandsCLRC control bitcontr
- Page 251 and 252:
SyntaxOperandsCMPLNoneOpcode 15 14
- Page 253 and 254:
CyclesCycles for a Single Instructi
- Page 255 and 256:
DescriptionIf a long immediate cons
- Page 257 and 258:
SyntaxOperandsCRGTNoneOpcode 15 14
- Page 259 and 260:
SyntaxOperandsCRLTNoneOpcode 15 14
- Page 261 and 262:
Syntax Direct: DMOV dmaIndirect: DM
- Page 263 and 264:
SyntaxOperandsEXARNoneOpcode 15 14
- Page 265 and 266:
SyntaxOperandsIDLE2NoneOpcode 15 14
- Page 267 and 268:
CyclesCycles for a Single Instructi
- Page 269 and 270:
The reserved interrupt vectors can
- Page 271 and 272:
Syntax Direct: LACC dma [,shift]Ind
- Page 273 and 274:
Example 1 LACC DAT6,4 ;(DP = 8, SXM
- Page 275 and 276:
CyclesFor the short immediate addre
- Page 277 and 278:
Syntax Direct: LACT dmaIndirect: LA
- Page 279 and 280:
Syntax Direct: LAMM dmaIndirect: LA
- Page 281 and 282:
Syntax Direct: LAR ARx, dmaIndirect
- Page 283 and 284:
Cycles for a Single Instruction (sh
- Page 285 and 286:
CyclesFor the short immediate addre
- Page 287 and 288:
Syntax Direct: LMMR dma, #addrIndir
- Page 289 and 290:
Example 1Example 2LMMR DBMR,#300hBe
- Page 291 and 292:
Example 1 LPH DAT0 ;(DP = 4)Before
- Page 293 and 294:
Words 1CyclesCycles for a Single In
- Page 295 and 296:
Syntax Direct: LT dmaIndirect: LT {
- Page 297 and 298:
Syntax Direct: LTA dmaIndirect: LTA
- Page 299 and 300:
Syntax Direct: LTD dmaIndirect: LTD
- Page 301 and 302:
Example 2 LTD *,AR3 ;(TRM = 0)Befor
- Page 303 and 304:
CyclesCycles for a Single Instructi
- Page 305 and 306:
CyclesCycles for a Single Instructi
- Page 307 and 308:
Words 2contents of the dma are mult
- Page 309 and 310:
Example 1 MAC 0FF00h,02h ;(DP = 6,
- Page 311 and 312:
DescriptionThe contents of the prod
- Page 313 and 314:
Cycles for a Repeat (RPT) Execution
- Page 315 and 316:
Syntax Direct: MADD dmaIndirect: MA
- Page 317 and 318:
Operand1: DARAM/ROM2: External1: SA
- Page 319 and 320:
Syntax Direct: MADS dmaIndirect: MA
- Page 321 and 322:
Cycles for a Repeat (RPT) Execution
- Page 323 and 324:
Syntax Direct: MAR dmaIndirect: MAR
- Page 325 and 326:
Syntax Direct: MPY dmaIndirect:MPY
- Page 327 and 328:
Example 1 MPY DAT13 ;(DP = 8)Before
- Page 329 and 330:
CyclesCycles for a Single Instructi
- Page 331 and 332:
CyclesCycles for a Single Instructi
- Page 333 and 334:
CyclesCycles for a Single Instructi
- Page 335 and 336:
Example 2 NEG ;(OVM = 0)Before Inst
- Page 337 and 338:
SyntaxOperandsNOPNoneOpcode 15 14 1
- Page 339 and 340:
The NORM instruction executes the a
- Page 341 and 342:
Syntax Direct: OPL [#lk], dmaIndire
- Page 343 and 344:
Example 1Example 2Example 3Example
- Page 345 and 346:
DescriptionIf a long immediate cons
- Page 347 and 348:
SyntaxOperandsORBNoneOpcode 15 14 1
- Page 349 and 350:
CyclesCycles for a Single Instructi
- Page 351 and 352:
SyntaxOperandsPOPNoneOpcode 15 14 1
- Page 353 and 354:
Syntax Direct: POPD dmaIndirect: PO
- Page 355 and 356:
Syntax Direct: PSHD dmaIndirect: PS
- Page 357 and 358:
SyntaxOperandsPUSHNoneOpcode 15 14
- Page 359 and 360:
SyntaxOperandsRETNoneOpcode 15 14 1
- Page 361 and 362:
ExampleRETC GEQ,NOV ;A return, RET,
- Page 363 and 364:
Example RETCD C ;A return, RET, is
- Page 365 and 366:
SyntaxOperandsRETENoneOpcode 15 14
- Page 367 and 368:
SyntaxOperandsROLNoneOpcode 15 14 1
- Page 369 and 370:
SyntaxOperandsRORNoneOpcode 15 14 1
- Page 371 and 372:
Syntax Direct: RPT dmaIndirect:RPT
- Page 373 and 374:
Example 3Example 4RPT #1 ;Repeat ne
- Page 375 and 376:
CyclesThe RPTB instruction is not r
- Page 377 and 378:
SyntaxOperandsSACBNoneOpcode 15 14
- Page 379 and 380:
Example 1 SACH DAT10,1 ;(DP = 4)Bef
- Page 381 and 382:
Example 1 SACL DAT11,1 ;(DP = 4)Bef
- Page 383 and 384:
Example 1 SAMM PRD ;(DP = 6)Before
- Page 385 and 386:
CyclesCycles for a Single Instructi
- Page 387 and 388:
Example 2 SATH ;(SXM = 1)Before Ins
- Page 389 and 390:
SyntaxOperandsSBBNoneOpcode 15 14 1
- Page 391 and 392:
Syntax SBRK #kOperands 0 ≤ k ≤
- Page 393 and 394:
An IDLE instruction must not follow
- Page 395 and 396:
SyntaxOperandsSFLBNoneOpcode 15 14
- Page 397 and 398:
Example 1 SFR ;(SXM = 0)Before Inst
- Page 399 and 400:
CyclesCycles for a Single Instructi
- Page 401 and 402:
CyclesCycles for a Single Instructi
- Page 403 and 404:
SyntaxOperandsSPACNoneOpcode 15 14
- Page 405 and 406:
Example 1 SPH DAT3 ;(DP = 4, PM = 0
- Page 407 and 408:
Example 1 SPL DAT5 ;(DP = 1, PM = 2
- Page 409 and 410:
SyntaxSPM constantOperands 0 ≤ co
- Page 411 and 412:
CyclesCycles for a Single Instructi
- Page 413 and 414:
CyclesCycles for a Single Instructi
- Page 415 and 416:
CyclesCycles for a Single Instructi
- Page 417 and 418:
Short immediate addressing:(PC) + 1
- Page 419 and 420:
Example 2 SUB *-,1,AR0 ;(SXM = 0)Be
- Page 421 and 422:
Cycles for a Repeat (RPT) Execution
- Page 423 and 424:
Words 1CyclesCycles for a Single In
- Page 425 and 426:
CyclesCycles for a Single Instructi
- Page 427 and 428:
CyclesCycles for a Single Instructi
- Page 429 and 430:
CyclesCycles for a Single Instructi
- Page 431 and 432:
Syntax Direct: TBLW dmaIndirect: TB
- Page 433 and 434:
OperandSource: SARAMDestination: SA
- Page 435 and 436:
Syntax XC n ,cond [,cond1] [,...]Op
- Page 437 and 438:
Syntax Direct: XOR dmaIndirect:XOR
- Page 439 and 440:
Example 1 XOR DAT127 ;(DP = 511)Bef
- Page 441 and 442:
Syntax Direct: XPL [#lk,] dmaIndire
- Page 443 and 444:
Example 1 XPL #100h,DAT60 ;(DP = 0)
- Page 445 and 446:
Example 1 ZALR DAT3 ;(DP = 32)Befor
- Page 447 and 448:
SyntaxOperandsZPRNoneOpcode 15 14 1
- Page 449 and 450:
Pipeline Structure7.1 Pipeline Stru
- Page 451 and 452:
Pipeline OperationAssume memory loc
- Page 453 and 454:
Pipeline OperationCycle 5: F) Fetch
- Page 455 and 456:
Pipeline OperationR) Dummy operatio
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Pipeline OperationCycle 4: F) Fetch
- Page 459 and 460:
Pipeline OperationAssume memory loc
- Page 461 and 462:
Pipeline OperationCycle 16: F)Fetch
- Page 463 and 464:
Pipeline OperationCycle 7: F) Fetch
- Page 465 and 466:
Pipeline OperationCycle 6: F) Fetch
- Page 467 and 468:
Pipeline OperationCycle 6: F) Fetch
- Page 469 and 470:
Pipeline OperationAssume memory loc
- Page 471 and 472:
Pipeline Latency7.3 Pipeline Latenc
- Page 473 and 474:
7-26
- Page 475 and 476:
Memory Space Overview8.1 Memory Spa
- Page 477 and 478:
Memory Space OverviewFigure 8-1.
- Page 479 and 480:
Memory Space OverviewFigure 8-5.
- Page 481 and 482:
0 ÁÁÁÁÁ1 ÁÁÁÁÁProgram Mem
- Page 483 and 484:
Program MemoryTable 8-4. ’C53 and
- Page 485 and 486:
ÁÁÁÁÁ2ÁÁÁÁÁÁÁ2ÁÁÁÁ
- Page 487 and 488:
Program MemoryInstruction addresses
- Page 489 and 490:
Local Data MemoryTable 8-8. ’C50
- Page 491 and 492:
Local Data Memory The 32-word scrat
- Page 493 and 494:
Global Data Memory8.4 Global Data M
- Page 495 and 496:
Input/Output (I/O) Space8.5 Input/O
- Page 497 and 498:
Direct Memory Access (DMA)8.6.2 Ext
- Page 499 and 500:
Memory Management8.7 Memory Managem
- Page 501 and 502:
Memory Management8.7.2.2 Moving Dat
- Page 503 and 504:
Memory ManagementExample 8-4. Movin
- Page 505 and 506:
Boot Loader8.8 Boot LoaderSeveral o
- Page 507 and 508:
Boot LoaderAn alternative to the HP
- Page 509 and 510:
Boot Loader8.8.3.2 8-Bit Word Paral
- Page 511 and 512:
Boot Loaderother means (for example
- Page 513 and 514:
External Parallel Interface Operati
- Page 515 and 516:
Software Wait-State Generation8.10
- Page 517 and 518:
ÁÁÁ3233 ÁÁÁ3637 ÁÁÁÁÁÁ4
- Page 519 and 520:
ÁÁÁ9293 ÁÁÁ94 ÁÁÁPeriphera
- Page 521 and 522:
Peripheral Control9.1.3 Peripheral
- Page 523 and 524:
Clock Generator9.2.2 PLL Clock Opti
- Page 525 and 526:
5 ÁÁTRB ÁÁTimerFigure 9-3. Time
- Page 527 and 528:
TimerExample 9-1. Code Initializati
- Page 529 and 530:
Software-Programmable Wait-State Ge
- Page 531 and 532:
Software-Programmable Wait-State Ge
- Page 533 and 534:
Software-Programmable Wait-State Ge
- Page 535 and 536:
General-Purpose I/O Pins9.5 General
- Page 537 and 538:
Parallel I/O Ports9.6 Parallel I/O
- Page 539 and 540:
Serial Port Interface9.7.1 Serial P
- Page 541 and 542:
Serial Port InterfaceTable 9-12.Ser
- Page 543 and 544:
ÁÁÁÁÁÁÁÁÁÁ14 13 12 9 Free
- Page 545 and 546:
Serial Port InterfaceTable 9-13.Ser
- Page 547 and 548:
Serial Port InterfaceDLB BitFigure
- Page 549 and 550:
Serial Port InterfaceXRST and RRST
- Page 551 and 552:
Serial Port InterfaceWhen XSREMPTY
- Page 553 and 554:
Serial Port InterfaceFigure 9-16. B
- Page 555 and 556:
Serial Port InterfaceFigure 9-18. B
- Page 557 and 558:
Serial Port InterfaceUnlike transmi
- Page 559 and 560:
Serial Port InterfaceAs shown in Fi
- Page 561 and 562:
Serial Port InterfaceFigure 9-26. C
- Page 563 and 564:
Serial Port InterfaceTransmitter ex
- Page 565 and 566:
Serial Port InterfaceAnother cause
- Page 567 and 568:
Serial Port InterfaceExample 9-4 sh
- Page 569 and 570:
Buffered Serial Port (BSP) Interfac
- Page 571 and 572:
Buffered Serial Port (BSP) Interfac
- Page 573 and 574:
Buffered Serial Port (BSP) Interfac
- Page 575 and 576:
Buffered Serial Port (BSP) Interfac
- Page 577 and 578:
Buffered Serial Port (BSP) Interfac
- Page 579 and 580:
Buffered Serial Port (BSP) Interfac
- Page 581 and 582:
Buffered Serial Port (BSP) Interfac
- Page 583 and 584:
Buffered Serial Port (BSP) Interfac
- Page 585 and 586:
Buffered Serial Port (BSP) Interfac
- Page 587 and 588:
Buffered Serial Port (BSP) Interfac
- Page 589 and 590:
Time-Division Multiplexed (TDM) Ser
- Page 591 and 592:
Time-Division Multiplexed (TDM) Ser
- Page 593 and 594:
X2 ÁÁXRDY RRDY ÁÁ ÁÁÁS2 ÁÁ
- Page 595 and 596:
Time-Division Multiplexed (TDM) Ser
- Page 597 and 598:
Time-Division Multiplexed (TDM) Ser
- Page 599 and 600:
Time-Division Multiplexed (TDM) Ser
- Page 601 and 602:
Time-Division Multiplexed (TDM) Ser
- Page 603 and 604:
Host Port InterfaceThe HPI provides
- Page 605 and 606:
Host Port InterfaceTable 9-24 summa
- Page 607 and 608:
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
- Page 609 and 610:
Host Port InterfaceTable 9-26.HPI I
- Page 611 and 612:
HINT ÁÁÁ0 ÁÁÁÁÁÁ11 ÁÁÁ1
- Page 613 and 614:
Host Port InterfaceFigure 9-52. HPI
- Page 615 and 616:
Internal HPI RAM read complete ÁÁ
- Page 617 and 618:
Host Port InterfaceHost Port Interf
- Page 619 and 620:
Comes out of reset ÁÁÁÁHost Por
- Page 621 and 622:
100-Pin QFP Pinout (’C52)A.1 100-
- Page 623 and 624:
100-Pin TQFP Pinout (’C51, ’C52
- Page 625 and 626:
128-Pin TQFP Pinout (’LC57)A.3 12
- Page 627 and 628:
132-Pin BQFP Pinout (’C50, ’C51
- Page 629 and 630:
144-Pin TQFP Pinout (’C57S)A.5 14
- Page 631 and 632:
100-Pin TQFP Device-Specific Pinout
- Page 633 and 634:
Signal DescriptionsTable A-8. Memor
- Page 635 and 636:
Signal DescriptionsTable A-10.Initi
- Page 637 and 638:
Signal DescriptionsTable A-13.Oscil
- Page 639 and 640:
Signal DescriptionsTable A-15.Seria
- Page 641 and 642:
Signal DescriptionsTable A-17.Host
- Page 643 and 644:
Signal DescriptionsTable A-18.Emula
- Page 645 and 646:
Cycle Class-to-Instruction Set Summ
- Page 647 and 648:
Cycle Class-to-Instruction Set Summ
- Page 649 and 650:
Instruction Set-to-Cycle Class Summ
- Page 651 and 652:
Instruction Set-to-Cycle Class Summ
- Page 653 and 654:
Instruction Set-to-Cycle Class Summ
- Page 655 and 656:
Instruction Set-to-Cycle Class Summ
- Page 657 and 658:
Package and Pin LayoutC.1 Package a
- Page 659 and 660:
Package and Pin LayoutWhen a ’C25
- Page 661 and 662:
Package and Pin LayoutThe ’C5x MP
- Page 663 and 664:
TimingThe ’C5x has two additional
- Page 665 and 666:
On-Chip Peripheral InterfacingC.3 O
- Page 667 and 668:
’C2x-to-’C5x Instruction SetC.4
- Page 669 and 670:
’C2x-to-’C5x Instruction SetTab
- Page 671 and 672:
’C2x-to-’C5x Instruction SetTab
- Page 673 and 674:
’C2x-to-’C5x Instruction SetTab
- Page 675 and 676:
Appendix DADesign Considerations fo
- Page 677 and 678:
Bus ProtocolD.2 Bus ProtocolThe IEE
- Page 679 and 680:
Emulator Cable PodFigure D-2. Emula
- Page 681 and 682:
Target System Test ClockD.5 Target
- Page 683 and 684:
Connections Between the Emulator an
- Page 685 and 686:
Emulation Timing CalculationsD.8 Em
- Page 687 and 688:
Emulation Timing CalculationsCase 4
- Page 689 and 690:
Appendix EAMemories, Sockets, and C
- Page 691 and 692:
CrystalsE.3 CrystalsThis section li
- Page 693 and 694:
Appendix FASubmitting ROM Codes to
- Page 695 and 696:
TMS320 Development FlowF.2 TMS320 D
- Page 697 and 698:
Appendix GADevelopment Support and
- Page 699 and 700:
Development SupportG.1.3Technical T
- Page 701 and 702:
Part Order InformationG.2.2Device N
- Page 703 and 704:
Part Order InformationTable G-1. TM
- Page 705 and 706:
Hewlett-Packard E2442A Preprocessor
- Page 707 and 708:
Appendix HAGlossaryAA0-A15:ABU:ACC:
- Page 709 and 710:
Glossaryautobuffering unit (ABU): A
- Page 711 and 712:
GlossaryBSP address transmit regist
- Page 713 and 714:
Glossarycircular buffer 1 start reg
- Page 715 and 716:
Glossarydata receive shift register
- Page 717 and 718:
GlossaryFFT:FIG:FO:See fast Fourier
- Page 719 and 720:
Glossaryhost port interface (HPI):
- Page 721 and 722:
Glossaryinterrupt mode (INTM) bit:
- Page 723 and 724:
GlossaryOoff-chip:on-chip:A device
- Page 725 and 726:
Glossaryprogram/data wait-state reg
- Page 727 and 728:
Glossaryserial port control registe
- Page 729 and 730:
GlossaryTDM data (TDAT): A single,
- Page 731 and 732:
Glossarytimer prescaler counter (PS
- Page 733 and 734:
GlossaryXXF:XH:XINT:See external fl
- Page 735 and 736:
Summary of Updates in This Document
- Page 737 and 738:
Summary of Updates in This Document
- Page 739 and 740:
Summary of Updates in This Document
- Page 741 and 742:
Summary of Updates in This Document
- Page 743 and 744:
Summary of Updates in This Document
- Page 745 and 746:
Summary of Updates in This Document
- Page 747 and 748:
Summary of Updates in This Document
- Page 749 and 750:
Summary of Updates in This Document
- Page 751 and 752:
Summary of Updates in This Document
- Page 753 and 754:
Summary of Updates in This Document
- Page 755 and 756:
Index’C2x instruction compatibili
- Page 757 and 758:
BCNDD instructiondescription 6-61ex
- Page 759 and 760:
circular buffer 2 auxiliary registe
- Page 761 and 762:
frame synchronization mode (FSM) bi
- Page 763 and 764:
internal hardware summary 3-2 to 3-
- Page 765 and 766:
MP/MC bit 4-9, 8-7, H-16MP/MC pin 8
- Page 767 and 768:
product register (PREG) 3-7, 3-24,
- Page 769 and 770:
SSACB instructiondescription 6-221s
- Page 771 and 772:
status register 1 (ST1) (continued)
- Page 773 and 774:
TMS320C5x (continued)compatibility
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