TMS320C5X USER'S GUIDE

Chapter 2Architectural OverviewThis chapter provides an overview of the architectural structure of the ’C5x,which consists of the buses, on-chip memory, central processing unit (CPU),and on-chip peripherals.The ’C5x uses an advanced, modified Harvard-type architecture based on the’C25 architecture and maximizes processing power with separate buses forprogram memory and data memory. The instruction set supports data transfersbetween the two memory spaces. Figure 2–1 shows a functional blockdiagram of the ’C5x.All ’C5x DSPs have the same CPU structure; however, they have differenton-chip memory configurations and on-chip peripherals.TopicPage2.1 Bus Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.3 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62.4 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.5 Test/Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11Architectural Overview2-1