TMS320C5X USER'S GUIDE

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Tables9–14 Serial Port Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9379–15 Buffered Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9559–16 Differences Between SP and BSP Operation in Standard Mode . . . . . . . . . . . . . . . . . . . 9569–17 BSP Control Extension Register (SPCE) Bit Summary — Serial Port Control Bits . . . . 9589–18 Buffered Serial Port Word Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9599–19 Autobuffering Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9609–20 BSP Control Extension Register (SPCE) Bit Summary — ABU Control Bits . . . . . . . . . 9649–21 TDM Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9759–22 Interprocessor Communications Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9839–23 TDM Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9839–24 HPI Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9909–25 HPI Signal Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9919–26 HPI Input Control Signals Function Selection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 9949–27 HPI Control Register (HPIC) Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9959–28 HPIC Host/’C5x Read/Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9969–29 Wait-State Generation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9999–30 Initialization of BOB and HPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91009–31 Read Access to HPI with Autoincrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91009–32 Write Access to HPI with Auto-Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91019–33 Sequence of Entering and Exiting IDLE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91039–34 HPI Operation During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9104A–1 Signal/Pin Assignments for the ’C52 in 100-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A3A–2 Signal/Pin Assignments for the ’C51, ’C52, ’C53S, and ’LC56 in 100-Pin TQFP . . . . . . . A5A–3 Signal/Pin Assignments for the ’LC57 in 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . A7A–4 Signal/Pin Assignments for the ’C50, ’C51, and ’C53 in 132-Pin BQFP . . . . . . . . . . . . . . . A9A–5 Signal/Pin Assignments for the ’C57S in 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . A11A–6 Device-Specific Pin/Signal Assignments for the ’C51, ’C52, ’C53S, and ’LC56in 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A12A–7 Address and Data Bus Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A13A–8 Memory Control Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A14A–9 Multiprocessing Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A15A–10 Initialization, Interrupt, and Reset Operations Signal Descriptions . . . . . . . . . . . . . . . . . . A16A–11 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A16A–12 Oscillator/Timer Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A17A–13 Oscillator/Timer Standard Options (’C50, ’C51, C52, ’C53, and ’C53S Only) . . . . . . . . . A18A–14 Oscillator/Timer Expanded Options (’LC56, ’C57S, and ’LC57 Only) . . . . . . . . . . . . . . . . A19A–15 Serial Port Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A20A–16 Buffered Serial Port Interface Signal Descriptions (’LC56 and ’C57 Only) . . . . . . . . . . . . A21A–17 Host Port Interface Signal Descriptions (’C57 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A22A–18 Emulation/Testing Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A24B–1 Cycle Class-to-Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B2B–2 Instruction Set-to-Cycle Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B5C–1 TMS320C2x Versus TMS320C5x for the ADD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . C12C–2 TMS320C2x to TMS320C5x Serial Port Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C13xxx
TablesC–3 TMS320C2x-to-TMS320C5x Accumulator Memory Reference Instructions . . . . . . . . . . C14C–4 TMS320C2x-to-TMS320C5x Auxiliary Registers and Data Memory PagePointer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C15C–5 TMS320C2x-to-TMS320C5x TREG0, PREG, and Multiply Instructions . . . . . . . . . . . . . . C16C–6 TMS320C2x-to-TMS320C5x Branch and Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . C17C–7 TMS320C2x-to-TMS320C5x I/O and Data Memory Operation Instructions . . . . . . . . . . . C18C–8 TMS320C2x-to-TMS320C5x Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C19D–1 XDS510 Header Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D2D–2 Emulator Cable Pod Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D6E–1 Commonly Used Crystal Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E3G–1 TMS320C5x Development Support Tools Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . G7Contentsxxxi
Page 2 and 3: IMPORTANT NOTICETexas Instruments (
Page 4 and 5: Notational How to UseConventionsThi
Page 6 and 7: Information About Cautions and Warn
Page 8 and 9: Technical Related Documentation Art
Page 10 and 11: Technical Articles17) Lovrich, A.,
Page 12 and 13: Technical Articles8) Rabiner, L.R.,
Page 14 and 15: Technical Articles6) Lovrich, A. an
Page 16 and 17: If You Need AssistanceIf You Need A
Page 18: Contents3 Central Processing Unit (
Page 21 and 22: Contents8.6.2 External DMA . . . .
Page 23 and 24: ContentsC.2.2 Pipeline . . . . . .
Page 25 and 26: FiguresFigures1-1 Evolution of the
Page 27 and 28: Figures9-31 SP/BSP Transmitter Func
Page 29: Tables6-10 Control Instructions . .
Page 33 and 34: Examples8-2 Moving External Data to
Page 35 and 36: Chapter 1IntroductionThis user’s
Page 37 and 38: TMS320 Family OverviewFigure 1-1. E
Page 39 and 40: TMS320C5x Overview1.2 TMS320C5x Ove
Page 41 and 42: TMS320C5x Key Features1.3 TMS320C5x
Page 43 and 44: TMS320C5x Key Features On-chip peri
Page 45 and 46: Chapter 2Architectural OverviewThis
Page 47 and 48: Bus Structure2.1 Bus StructureSepar
Page 49 and 50: Central Processing Unit (CPU)2.2.3
Page 51 and 52: On-Chip Memoryblock B0 can be confi
Page 53 and 54: On-Chip Peripherals2.4.4 Parallel I
Page 55 and 56: Test/Emulation2.5 Test/EmulationOn
Page 57 and 58: Chapter 3Central Processing Unit (C
Page 59 and 60: Functional OverviewFigure 3-1. Bloc
Page 61 and 62: Functional OverviewTable 3-1. ’C5
Page 63 and 64: Central Arithmetic Logic Unit (CALU
Page 71 and 72: Parallel Logic Unit (PLU)3.3 Parall
Page 73 and 74: Auxiliary Register Arithmetic Unit
Page 75 and 76: Auxiliary Register Arithmetic Unit
Page 77 and 78: Summary of Registers3.5 Summary of
Page 79 and 80: Summary of Registers3.5.8 Global Me
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Summary of Registers3.5.18 Status R
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Chapter 4Program ControlProgram con
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Program Counter (PC)Table 4-1. Addr
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Program-Memory Address Generation4.
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Status and Control RegistersFigure
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Status and Control RegistersTable 4
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Status and Control RegistersFigure
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CNF ÁÁStatus and Control Register
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Status and Control RegistersTable 4
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Conditional Operations4.5 Condition
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Conditional OperationsYou can combi
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Conditional OperationsThe condition
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Single Instruction Repeat FunctionT
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Block Repeat Function4.7 Block Repe
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Block Repeat Functionprocessor will
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Block Repeat FunctionExample 4-12.
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---ÁÁÁÁÁ--- ÁÁÁÁÁ---ÁÁ
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Interrupts4.8.3 Interrupt Flag Regi
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Interrupts4.8.6 Nonmaskable Interru
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InterruptsExample 4-13. Modifying R
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Reset4.9 ResetReset (RS) is a nonma
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ResetTable 4-16.Peripheral Register
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ResetFigure 4-10. RS and HOLD Inter
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Power-Down Mode4.10.3 Power Down Us
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Chapter 5Addressing ModesThis chapt
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Direct AddressingNote:The DP is not
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Indirect Addressing5.2.1 Indirect A
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Indirect Addressing*0- Decrement by
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Indirect AddressingTable 5-2. Indir
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1 1 0 0 ÁÁ ÁÁÁÁ ÁÁ1 ÁÁ0
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Indirect AddressingExample 5-10. Se
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Immediate Addressing5.3.2 Long Imme
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Dedicated-Register Addressing5.4 De
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Memory-Mapped Register Addressing5.
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Circular Addressing5.6 Circular Add
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Chapter 6Assembly Language Instruct
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Instruction Set Symbols and Notatio
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Instruction Set Summaryextra cycle
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Instruction Set SummaryTable 6-4. A
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Instruction Set SummaryTable 6-5. A
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Instruction Set SummaryTable 6-7. T
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Instruction Set SummaryTable 6-7. T
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Instruction Set SummaryTable 6-8. B
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Instruction Set SummaryTable 6-10.C
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Instruction Set Descriptions6.3 Ins
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Execution(PC) + 1 → PC(ACC) + (dm
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Table 6-11 lists the on-chip single
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SyntaxOperandsABSNoneOpcode 15 14 1
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SyntaxOperandsADCBNoneOpcode 15 14
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Short immediate addressing:(PC) + 1
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Example 2 ADD *+,0,AR0Before Instru
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Syntax Direct: ADDC dmaIndirect: AD
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Syntax Direct: ADDS dmaIndirect: AD
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Syntax Direct: ADDT dmaIndirect: AD
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Syntax ADRK #kOperands 0 ≤ k ≤
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WordsCycles1 (Direct or indirect ad
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SyntaxOperandsANDBNoneOpcode 15 14
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Syntax Direct: APL [#lk,] dmaIndire
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Example 1 APL #0023h,DAT96 ;(DP = 0
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SyntaxOperandsBACCNoneOpcode 15 14
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Syntax BANZ pma [, {ind} [,ARn ]]Op
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Syntax BANZD pma [, {ind} [,ARn ]]O
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Syntax BCND pma, cond [,cond1] [,..
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Syntax BCNDD pma, cond [,cond1] [,.
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Syntax BD pma [, {ind} [,ARn ]]Oper
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Words 1CyclesCycles for a Single In
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Words 1You can maintain software co
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Indirect addressing with DEST speci
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Cycles for a Repeat (RPT) Execution
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Example 1 BLDD #300h,20h ;(DP = 6)B
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Syntax General syntax: BLPD src, ds
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OperandSource: SARAMDestination: Ex
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OperandSource: ExternalDestination:
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SyntaxBSAR shiftOperands 1 ≤ shif
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SyntaxOperandsCALADNoneOpcode 15 14
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SyntaxCALLD pma [,{ind} [,ARn]]Oper
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Syntax CC pma cond [,cond1] [,...]O
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Syntax CCD pma cond [,cond1] [,...]
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SyntaxOperandsCLRC control bitcontr
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SyntaxOperandsCMPLNoneOpcode 15 14
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CyclesCycles for a Single Instructi
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DescriptionIf a long immediate cons
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SyntaxOperandsCRGTNoneOpcode 15 14
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SyntaxOperandsCRLTNoneOpcode 15 14
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Syntax Direct: DMOV dmaIndirect: DM
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SyntaxOperandsEXARNoneOpcode 15 14
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SyntaxOperandsIDLE2NoneOpcode 15 14
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The reserved interrupt vectors can
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Syntax Direct: LACC dma [,shift]Ind
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Example 1 LACC DAT6,4 ;(DP = 8, SXM
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CyclesFor the short immediate addre
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Syntax Direct: LACT dmaIndirect: LA
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Syntax Direct: LAMM dmaIndirect: LA
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Syntax Direct: LAR ARx, dmaIndirect
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Cycles for a Single Instruction (sh
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CyclesFor the short immediate addre
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Syntax Direct: LMMR dma, #addrIndir
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Example 1Example 2LMMR DBMR,#300hBe
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Example 1 LPH DAT0 ;(DP = 4)Before
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Syntax Direct: LT dmaIndirect: LT {
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Syntax Direct: LTA dmaIndirect: LTA
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Syntax Direct: LTD dmaIndirect: LTD
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Example 2 LTD *,AR3 ;(TRM = 0)Befor
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Words 2contents of the dma are mult
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Example 1 MAC 0FF00h,02h ;(DP = 6,
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DescriptionThe contents of the prod
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Syntax Direct: MADD dmaIndirect: MA
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Operand1: DARAM/ROM2: External1: SA
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Syntax Direct: MADS dmaIndirect: MA
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Syntax Direct: MAR dmaIndirect: MAR
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Syntax Direct: MPY dmaIndirect:MPY
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Example 1 MPY DAT13 ;(DP = 8)Before
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Example 2 NEG ;(OVM = 0)Before Inst
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SyntaxOperandsNOPNoneOpcode 15 14 1
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The NORM instruction executes the a
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Syntax Direct: OPL [#lk], dmaIndire
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Example 1Example 2Example 3Example
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DescriptionIf a long immediate cons
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SyntaxOperandsORBNoneOpcode 15 14 1
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SyntaxOperandsPOPNoneOpcode 15 14 1
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Syntax Direct: POPD dmaIndirect: PO
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Syntax Direct: PSHD dmaIndirect: PS
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SyntaxOperandsPUSHNoneOpcode 15 14
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SyntaxOperandsRETNoneOpcode 15 14 1
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ExampleRETC GEQ,NOV ;A return, RET,
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Example RETCD C ;A return, RET, is
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SyntaxOperandsRETENoneOpcode 15 14
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SyntaxOperandsROLNoneOpcode 15 14 1
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SyntaxOperandsRORNoneOpcode 15 14 1
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Syntax Direct: RPT dmaIndirect:RPT
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Example 3Example 4RPT #1 ;Repeat ne
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CyclesThe RPTB instruction is not r
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SyntaxOperandsSACBNoneOpcode 15 14
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Example 1 SACH DAT10,1 ;(DP = 4)Bef
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Example 1 SACL DAT11,1 ;(DP = 4)Bef
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Example 1 SAMM PRD ;(DP = 6)Before
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Example 2 SATH ;(SXM = 1)Before Ins
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SyntaxOperandsSBBNoneOpcode 15 14 1
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Syntax SBRK #kOperands 0 ≤ k ≤
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An IDLE instruction must not follow
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SyntaxOperandsSFLBNoneOpcode 15 14
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Example 1 SFR ;(SXM = 0)Before Inst
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SyntaxOperandsSPACNoneOpcode 15 14
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Example 1 SPH DAT3 ;(DP = 4, PM = 0
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Example 1 SPL DAT5 ;(DP = 1, PM = 2
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SyntaxSPM constantOperands 0 ≤ co
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Short immediate addressing:(PC) + 1
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Example 2 SUB *-,1,AR0 ;(SXM = 0)Be
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Syntax Direct: TBLW dmaIndirect: TB
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OperandSource: SARAMDestination: SA
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Syntax XC n ,cond [,cond1] [,...]Op
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Syntax Direct: XOR dmaIndirect:XOR
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Example 1 XOR DAT127 ;(DP = 511)Bef
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Syntax Direct: XPL [#lk,] dmaIndire
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Example 1 XPL #100h,DAT60 ;(DP = 0)
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Example 1 ZALR DAT3 ;(DP = 32)Befor
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SyntaxOperandsZPRNoneOpcode 15 14 1
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Pipeline Structure7.1 Pipeline Stru
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Pipeline OperationAssume memory loc
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Pipeline OperationCycle 5: F) Fetch
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Pipeline OperationR) Dummy operatio
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Pipeline OperationCycle 16: F)Fetch
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Pipeline Latency7.3 Pipeline Latenc
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7-26
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Memory Space Overview8.1 Memory Spa
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Memory Space OverviewFigure 8-1.
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Memory Space OverviewFigure 8-5.
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0 ÁÁÁÁÁ1 ÁÁÁÁÁProgram Mem
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Program MemoryTable 8-4. ’C53 and
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ÁÁÁÁÁ2ÁÁÁÁÁÁÁ2ÁÁÁÁ
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Program MemoryInstruction addresses
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Local Data MemoryTable 8-8. ’C50
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Local Data Memory The 32-word scrat
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Global Data Memory8.4 Global Data M
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Input/Output (I/O) Space8.5 Input/O
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Direct Memory Access (DMA)8.6.2 Ext
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Memory Management8.7 Memory Managem
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Memory Management8.7.2.2 Moving Dat
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Memory ManagementExample 8-4. Movin
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Boot Loader8.8 Boot LoaderSeveral o
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Boot LoaderAn alternative to the HP
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Boot Loader8.8.3.2 8-Bit Word Paral
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Boot Loaderother means (for example
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External Parallel Interface Operati
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Software Wait-State Generation8.10
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ÁÁÁ3233 ÁÁÁ3637 ÁÁÁÁÁÁ4
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ÁÁÁ9293 ÁÁÁ94 ÁÁÁPeriphera
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Peripheral Control9.1.3 Peripheral
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Clock Generator9.2.2 PLL Clock Opti
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5 ÁÁTRB ÁÁTimerFigure 9-3. Time
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TimerExample 9-1. Code Initializati
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Software-Programmable Wait-State Ge
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General-Purpose I/O Pins9.5 General
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Parallel I/O Ports9.6 Parallel I/O
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Serial Port Interface9.7.1 Serial P
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Serial Port InterfaceTable 9-12.Ser
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ÁÁÁÁÁÁÁÁÁÁ14 13 12 9 Free
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Serial Port InterfaceTable 9-13.Ser
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Serial Port InterfaceDLB BitFigure
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Serial Port InterfaceXRST and RRST
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Serial Port InterfaceWhen XSREMPTY
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Serial Port InterfaceFigure 9-16. B
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Serial Port InterfaceFigure 9-18. B
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Serial Port InterfaceUnlike transmi
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Serial Port InterfaceAs shown in Fi
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Serial Port InterfaceFigure 9-26. C
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Serial Port InterfaceTransmitter ex
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Serial Port InterfaceAnother cause
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Serial Port InterfaceExample 9-4 sh
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Buffered Serial Port (BSP) Interfac
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Time-Division Multiplexed (TDM) Ser
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X2 ÁÁXRDY RRDY ÁÁ ÁÁÁS2 ÁÁ
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Host Port InterfaceThe HPI provides
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Host Port InterfaceTable 9-24 summa
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Host Port InterfaceTable 9-26.HPI I
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HINT ÁÁÁ0 ÁÁÁÁÁÁ11 ÁÁÁ1
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Host Port InterfaceFigure 9-52. HPI
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Internal HPI RAM read complete ÁÁ
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Host Port InterfaceHost Port Interf
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Comes out of reset ÁÁÁÁHost Por
Page 621 and 622:
100-Pin QFP Pinout (’C52)A.1 100-
Page 623 and 624:
100-Pin TQFP Pinout (’C51, ’C52
Page 625 and 626:
128-Pin TQFP Pinout (’LC57)A.3 12
Page 627 and 628:
132-Pin BQFP Pinout (’C50, ’C51
Page 629 and 630:
144-Pin TQFP Pinout (’C57S)A.5 14
Page 631 and 632:
100-Pin TQFP Device-Specific Pinout
Page 633 and 634:
Signal DescriptionsTable A-8. Memor
Page 635 and 636:
Signal DescriptionsTable A-10.Initi
Page 637 and 638:
Signal DescriptionsTable A-13.Oscil
Page 639 and 640:
Signal DescriptionsTable A-15.Seria
Page 641 and 642:
Signal DescriptionsTable A-17.Host
Page 643 and 644:
Signal DescriptionsTable A-18.Emula
Page 645 and 646:
Cycle Class-to-Instruction Set Summ
Page 647 and 648:
Cycle Class-to-Instruction Set Summ
Page 649 and 650:
Instruction Set-to-Cycle Class Summ
Page 651 and 652:
Page 653 and 654:
Page 655 and 656:
Page 657 and 658:
Package and Pin LayoutC.1 Package a
Page 659 and 660:
Package and Pin LayoutWhen a ’C25
Page 661 and 662:
Package and Pin LayoutThe ’C5x MP
Page 663 and 664:
TimingThe ’C5x has two additional
Page 665 and 666:
On-Chip Peripheral InterfacingC.3 O
Page 667 and 668:
’C2x-to-’C5x Instruction SetC.4
Page 669 and 670:
’C2x-to-’C5x Instruction SetTab
Page 671 and 672:
Page 673 and 674:
Page 675 and 676:
Appendix DADesign Considerations fo
Page 677 and 678:
Bus ProtocolD.2 Bus ProtocolThe IEE
Page 679 and 680:
Emulator Cable PodFigure D-2. Emula
Page 681 and 682:
Target System Test ClockD.5 Target
Page 683 and 684:
Connections Between the Emulator an
Page 685 and 686:
Emulation Timing CalculationsD.8 Em
Page 687 and 688:
Emulation Timing CalculationsCase 4
Page 689 and 690:
Appendix EAMemories, Sockets, and C
Page 691 and 692:
CrystalsE.3 CrystalsThis section li
Page 693 and 694:
Appendix FASubmitting ROM Codes to
Page 695 and 696:
TMS320 Development FlowF.2 TMS320 D
Page 697 and 698:
Appendix GADevelopment Support and
Page 699 and 700:
Development SupportG.1.3Technical T
Page 701 and 702:
Part Order InformationG.2.2Device N
Page 703 and 704:
Part Order InformationTable G-1. TM
Page 705 and 706:
Hewlett-Packard E2442A Preprocessor
Page 707 and 708:
Appendix HAGlossaryAA0-A15:ABU:ACC:
Page 709 and 710:
Glossaryautobuffering unit (ABU): A
Page 711 and 712:
GlossaryBSP address transmit regist
Page 713 and 714:
Glossarycircular buffer 1 start reg
Page 715 and 716:
Glossarydata receive shift register
Page 717 and 718:
GlossaryFFT:FIG:FO:See fast Fourier
Page 719 and 720:
Glossaryhost port interface (HPI):
Page 721 and 722:
Glossaryinterrupt mode (INTM) bit:
Page 723 and 724:
GlossaryOoff-chip:on-chip:A device
Page 725 and 726:
Glossaryprogram/data wait-state reg
Page 727 and 728:
Glossaryserial port control registe
Page 729 and 730:
GlossaryTDM data (TDAT): A single,
Page 731 and 732:
Glossarytimer prescaler counter (PS
Page 733 and 734:
GlossaryXXF:XH:XINT:See external fl
Page 735 and 736:
Summary of Updates in This Document
Page 737 and 738:
Page 739 and 740:
Page 741 and 742:
Page 743 and 744:
Page 745 and 746:
Page 747 and 748:
Page 749 and 750:
Page 751 and 752:
Page 753 and 754:
Page 755 and 756:
Index’C2x instruction compatibili
Page 757 and 758:
BCNDD instructiondescription 6-61ex
Page 759 and 760:
circular buffer 2 auxiliary registe
Page 761 and 762:
frame synchronization mode (FSM) bi
Page 763 and 764:
internal hardware summary 3-2 to 3-
Page 765 and 766:
MP/MC bit 4-9, 8-7, H-16MP/MC pin 8
Page 767 and 768:
product register (PREG) 3-7, 3-24,
Page 769 and 770:
SSACB instructiondescription 6-221s
Page 771 and 772:
status register 1 (ST1) (continued)
Page 773 and 774:
TMS320C5x (continued)compatibility
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TMS320C5X USER'S GUIDE

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