Lecture 6: Designing Combinational Logic Circuits

Lecture 6: Designing CombinationalLogic Circuits

Static CMOS Circuit1. At every point in time (except during the switchingtransients) each gate output is connected to eitherV DD or V ss via a low-resistive path.2. The outputs of the gates assume at all times the valueof the Boolean function, implemented by the circuit(ignoring, once again, the transient effects duringswitching periods).3. This is in contrast to the dynamic circuit class, whichrelies on temporary storage of signal values on thecapacitance of high impedance circuit nodes.

… …Static Complementary CMOSV DDIn1In2PUNPMOS onlyInNIn1In2InNPDNNMOS onlyF(In1,In2,…InN)PUN and PDN are dual logic networks

NMOS Transistorsin Series/Parallel ConnectionTransistors can be thought as a switch controlled by itsgate signalNMOS switch closes when switch control input is highABXYY = X if A and BAXBYY = X if A OR BNMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistorsin Series/Parallel ConnectionPMOS switch closes when switch control input is lowABXYY = X if A AND B = A + BAXBYY = X if A OR B = ABPMOS Transistors pass a “strong” 1 but a “weak” 0

Threshold DropsV DDV DD → 0PUNSV DDDD0 → V DDV GSSV DDV DD → |V Tp |0 → V DD -V TnC LC LPDNV DDDC LV GSSC LSD

Complementary CMOS Logic Style

Example Gate: NAND

Example Gate: NOR

Complex CMOS GateABCDDBACOUT = D + A • (B + C)

Cell Design• Standard Cells◦ General purpose logic◦ Can be synthesized◦ Same height, varying width• Datapath Cells◦ For regular, structured designs(arithmetic)◦ Includes some wiring in the cell◦ Fixed height and width

Standard CellsN WellV DDCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch =repetitive distance between objectsCell height is “12 pitch”2λInOutCell boundaryGNDRails ~10λ

Standard CellsV DD2-input NAND gateV DDABBOutAGND

Stick DiagramsContains no dimensionsRepresents relative positions of transistorsInverterV DDNAND2V DDOutOutGNDInGNDAB

Two Stick Layouts of !(C • (A + B))ACBA B CV DDV DDXXGNDGNDuninterrupted diffusion strip

Connection label layout

VDD, VSS and Output Labels

Interconnected

CMOS Properties• Full rail-to-rail swing; high noise margins• Logic levels not dependent upon the relative devicesizes; ratioless• Always a path to Vdd or Gnd in steady state; lowoutput impedance• Extremely high input resistance; nearly zero steadystateinput current• No direct path steady state between power andground; no static power dissipation• Propagation delay function of load capacitance andresistance of transistors

Switch Delay ModelAAR eqR p R pBA BR pAR n C LABR n C LARR nnCintAANAND2INVR pR pR nBC intC LNOR2

Input Pattern Effects on DelayAR pR nBR pC L• Delay is dependent onthe pattern of inputs• Low to high transition◦ both inputs go lowB• delay is 0.69 R p /2 C L◦ one input goes lowR nAC int• delay is 0.69 R p C L• High to low transition◦ both inputs go high• delay is 0.69 2R n C L

Delay Dependence on Input Patterns32.5A=B=1→0Input DataPatternDelay(psec)Voltage [V]21.510.5A=1 →0, B=1A=1, B=1→0A=B=0→1A=1, B=0→1A= 0→1, B=1A=B=1→0676461450A=1, B=1→080-0.50 100 200 300 400A= 1→0, B=181time [ps]NMOS = 0.5µm/0.25 µmPMOS = 0.75µm/0.25 µmC L = 100 fF

Transistor SizingR pR p2 A B 24BR n C L42ABR n R2nCint1AAR pR pR nBC int1C L

Transistor Sizing:a Complex CMOS GateA43BC8866D46OUT = D + A • (B + C)A2D1B2 C 2

Fan-In ConsiderationsABCDABC 3C LDistributed RC model(Elmore delay)CDC 2C 1t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L )Propagation delay deterioratesrapidly as a function of fan-in –quadratically in the worst case.

t p as a Function of Fan-Int p (psec)125010007505002500fan-int pHL t pt pLH2 4 6 8 10 12 14 16quadraticlinearGates with afan-ingreater than4 should beavoided.

t p as a Function of Fan-Outt p (psec)t p NOR2 t p NAND2t p INV2 4 6 8 10 12 14 16eff. fan-outAll gateshave thesame drivecurrent.Slope is afunction of“drivingstrength”

t p as a Function of Fan-In and Fan-Out• Fan-in: quadratic due to increasingresistance and capacitance• Fan-out: each additional fan-out gateadds two gate capacitances to C Lt p = a 1 FI + a 2 FI 2 + a 3 FO

Fast Complex Gates:Design Technique 1• Transistor sizing◦ as long as fan-out capacitance dominates• Progressive sizingIn NMNC LDistributed RC lineIn 3M3C 3M1 > M2 > M3 > … > MN(the fet closest to theoutput is the smallest)In 2In 1M2M1C 2C 1Can reduce delay by more than20%; decreasing gains astechnology shrinks

Fast Complex Gates:Design Technique 2• Transistor orderingcritical pathcritical pathIn 31In 21In 10→1charged0→1InM3 C 1LM3chargedC LIn 1M2 C 22 chargedM2 C 2 dischargedM1 chargedIn 31M1 C discharged1C 1delay determined by time todischarge C L , C 1 and C 2delay determined by time todischarge C L

Fast Complex Gates:Design Technique 3• Alternative logic structuresF = ABCDEFGH

Fast Complex Gates:Design Technique 4• Isolating fan-in from fan-out usingbuffer insertionC LC L

Fast Complex Gates:Design Technique 5• Reducing the voltage swingt pHL = 0.69 (3/4 (C L V DD )/ I DSATn )= 0.69 (3/4 (C L V swing )/ I DSATn )◦ linear reduction in delay◦ also reduces power consumption• But the following gate is much slower!• Or requires use of “sense amplifiers” on thereceiving end to restore the signal level(memory design)

Ratioed Logic

Ratioed LogicV DDV DDV DDResistiveLoadR LDepletionLoadV T < 0PMOSLoadFFV SSFIn 1In 2In 3PDNIn 1In 2In 3PDNIn 1In 2In 3PDNV SSV SSV SS(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSGoal: to reduce the number of devices over complementary CMOS

Ratioed LogicV DDResistiveLoadR L• N transistors + Load• V OH = V DDF• V OL =R PNR PN + R LIn 1In 2In 3PDN• Assymetrical response• Static power consumptionV SS• t pL= 0.69 R LC L

Active LoadsV DDV DDDepletionLoadV T < 0PMOSLoadFV SSFIn 1In 2In 3PDNIn 1In 2In 3PDNV SSV SSdepletion load NMOSpseudo-NMOS

Pseudo-NMOSV DDA B C DFC LV OH = V DD (similar to complementary CMOS)V2⎛k n( V –OL ⎞ kDDV Tn)V – p⎜OL------------- ⎟ = ------ ( V –⎝2 ⎠ 2 DDV Tp) 2V = V V OL( – DD T) 1– 1– k ------p(assuming that V = V = V )k T Tn Tp nSMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

Pseudo-NMOS VTC3.02.52.0W/L p = 4V ou t[V]1.51.0W/L p= 20.5W/L p= 0.5W/L p = 0.25W/L p= 10.00.0 0.5 1.0 1.5 2.0 2.5V in[V]

Improved LoadsV DDEnableM1M2M1 >> M2FA B C DC LAdaptive Load

Improved Loads (2)V DDV DDM1M2OutOutAABBPDN1PDN2V SSV SSDifferential Cascode Voltage Switch Logic (DCVSL)

DCVSL ExampleOutOutBB B BAAXOR-NXOR gate

DCVSL Transient Response2.5Volta ge [V]1.50.5A,BA,BA BA B-0.50 0.2 0.4 0.6 0.8 1.0Time [ns]

Pass-Transistor Logic

Pass-Transistor LogicBInputsSwitchNetworkOutABBOut• N transistors• No static consumption

NMOS-Only LogicV DDInx0.5µm/0.25µm1.5µm/ 0.25µm0.5 µm/ 0.25µmOutVoltage [V]3.02.01.0OutxIn0.00 0.5 1 1.5 2Time [ns]

NMOS-only SwitchC = 2.5VC = 2.5 VA = 2.5 VA = 2.5 VBM 2BM nC LM 1V B does not pull up to 2.5V, but 2.5V -V TNThreshold voltage loss causesstatic power consumptionNMOS has higher threshold than PMOS (body effect)

NMOS Only LogicSolution 1: Level Restoring TransistorLevel RestorerV DDV DDABM 2M rXM n OutM 1• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problem

Solution 2: Single Transistor Pass Gatewith V T =0V DD0V 2.5VV DDV DD0VOut2.5VWATCH OUT FOR LEAKAGE CURRENTS

Complementary Pass Transistor LogicAABBPass-TransistorNetworkF(a)AABBInversePass-TransistorNetworkFB B B BBBAAABF=ABBF=A+BAF=A⊕ΒÝAAA(b)BF=ABBF=A+BAF=A⊕ΒÝAND/NANDOR/NOREXOR/NEXOR

Solution 3: Transmission GateCCABABCCC = 2.5 VA = 2.5 VBC LC = 0 V

Resistance of Transmission Gate30R n2. 5 VRnResistance, ohms2010R pR n|| R p2.5 V0 VR pV ou t00.0 1.0 2.0V ou t, V

Pass-Transistor Based MultiplexerSSV DDIn 1 S S In 2SV DDAM 2SFM 1BSGND

Transmission Gate XORBM2BAM1BFBAM3/M4

Transmission Gate Full AdderV DDA AAPC iC iPV DDP S Sum GenerationV DDAPBBAPPC iC iC iASetupPV DDC oCarry GenerationSimilar delays for sum and carry

Dynamic Logic

Dynamic CMOS• In static circuits at every point in time(except when switching) the output isconnected to either GND or V DD via a lowresistance path.◦ fan-in of n requires 2n (n N-type + n P-type)devices• Dynamic circuits rely on the temporarystorage of signal values on the capacitanceof high impedance nodes.◦ requires on n + 2 (n+1 N-type + 1 P-type)transistors

Dynamic GateClkM pClkM pOutOutIn 1In 2In 3PDNC LABCClkM eClkM eTwo phase operationPrecharge (CLK = 0)Evaluate (CLK = 1)

Dynamic GateClkM pOutClkM poffon1OutIn 1In 2In 3PDNC LAB((AB)+C)CClkM eTwo phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)ClkM eoffon

Conditions on Output• Once the output of a dynamic gate isdischarged, it cannot be charged again untilthe next precharge operation.• Inputs to the gate can make at most onetransition during evaluation.• Output can be in the high impedance stateduring and after evaluation (PDN off), stateis stored on C L

Properties of Dynamic Gates• Logic function is implemented by the PDN only◦ number of transistors is N + 2 (versus 2N for static complementaryCMOS)• Full swing outputs (V OL = GND and V OH = V DD )• Faster switching speeds◦ reduced load capacitance due to lower input capacitance (C in )◦ reduced load capacitance due to smaller output loading (Cout)◦ no I sc , so all the current provided by PDN goes into discharging C L• Overall power dissipation usually higher than static CMOS• Low noise margin (NM L )• Needs a precharge/evaluate clock

Issues in Dynamic Design 1:Charge LeakageCLKClkM pOutAC LClkM eV OutEvaluatePrechargeLeakage sourcesDominant component is subthreshold current

Solution to Charge LeakageKeeperClkM pM kpABC LOutClkM eSame approach as level restorer for pass-transistor logic

Issues in Dynamic Design 2:Charge SharingClkAM pC LOutCharge stored originally onC L is redistributed (shared)over C L and C A leading toreduced robustnessB=0ClkM eC AC B

Charge Sharing ExampleClkAAOutC L =50fFC a =15fFB B B !BC b =15fFC c =15fFCCC d =10fFClk

Charge SharingV DDcase 1) if ∆V out < V TnClkM pOutC LV DD=C LV out ( t) + C a ( V DD– V Tn ( V X ))AM aXC L∆V outor= V out ( t) – V DD=C a–-------V (C DD– V Tn ( V X ))LB = 0M bC acase 2) if ∆V out > V TnClkM eC bC⎛ a∆V outV --------------------⎞= – DD ⎜C a+ C ⎟⎝ L ⎠

Solution to Charge RedistributionClkAM pM kpOutClkBClkM ePrecharge internal nodes using a clock-driven transistor(at the cost of increased area and power)

Issues in Dynamic Design 3:Backgate CouplingClkA=0M pC L1Out1=1C L2Out2 =0InB=0ClkM eDynamic NANDStatic NAND

Backgate Coupling Effect321ClkOut1Voltage0InOut2-10 2 Time, ns 4 6

Issues in Dynamic Design 4:Clock FeedthroughClkABClkM pM eC LOutCoupling between Out andClk input of the prechargedevice due to the gate todrain capacitance. Sovoltage of Out can riseabove V DD . The fast rising(and falling edges) of theclock couple to Out.

Clock FeedthroughClkOut2.5Clock feedthroughIn 1In 21.5VoltageIn 3In 4Clk0.5-0.5In &ClkOut0 0.5 Time, ns 1Clock feedthrough

Other Effects• Capacitive coupling• Substrate coupling• Minority charge injection• Supply noise (ground bounce)

Cascading Dynamic GatesVClkInM pClkOut1M pOut2ClkInClkM eClkM eOut1V TnOut2∆VtOnly 0 → 1 transitions allowed at inputs!

Domino LogicClkIn 1In 2M pPDN1 → 11 → 0Out1Clk0 → 00 → 1In 4M pM kpPDNOut2In 3In 5ClkM eClkM e

Why Domino?ClkIn iIn jClkPDNIn i PDN In i PDN In i PDNIn j In j In jLike falling dominos!

Properties of Domino Logic• Only non-inverting logic can beimplemented• Very high speed◦ static inverter can be skewed, only L-H transition◦ Input capacitance reduced – smaller logicaleffort

Designing with Domino LogicV DDV DDClkM pOut1ClkM pM rV DDOut2In 1In 2PDNPDNIn 4ClkIn 3Can be eliminated!ClkM eM eInputs = 0during precharge

np-CMOSClkIn 1M p1 → 11 → 0Out1ClkIn 4M ePUNIn 2In 3ClkPDNM eIn 5ClkM p0 → 00 → 1Out2(to PDN)Only 0 → 1 transitions allowed at inputs of PDNOnly 1 → 0 transitions allowed at inputs of PUN