Advanced 64-bit Microprocessors Product Family 79RC64574 ...

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79RC64574 79RC64575September 9, 1999: Made several changes in JTAG Interfacesection of Table 5. Added information on Pin 63 in Table 5.October 14, 1999: Revised data in the Power Consumption tablesfor RC64574 and RC64575.November 16, 1999: Added Power Curve graphs, revised data inSystem Interface Parameters table, added System Clock Jitter row toClock Parameter table.December 20, 1999: Table 7 “RC64574 128-Pin Package” on page12, Changed pin #75 function from Vcc to N.C.March 7, 2000: In Table 1, added “with DSP extensions” in the CPUrow under RC64574 and RC64575 columns and changed “by set” to “byline” in the Caches row for RC64574 and RC64575 columns. Addedrows in the Data Output and Data Output Hold rows in the System InterfaceParameters table. Removed references to 300 MHz, and changedbandwidth speed to 2GB/sec ond in Cache Memory section. Rev isedPower Curves.March 28, 2000: Replaced existing figure in Mode ConfigurationInterface Reset Sequence section with 3 reset figures. Revised valuesfor 250MHz in System Interface Parameters table. Changed Data Sheetfrom Preliminary to final.April 3, 2000: Deleted signal t DZ from Figure 6.April 25, 2001: In the Absolute Maximum Ratings table, changedupper voltage limit from 3.8 to 4.0V and removed “Vin should not exceedVcc +0.5 volts” from footnote #1. In DC Electrical Characteristics table,changed maximum value for Vih from 3.3 to 3.8V for all speeds.May 1, 2001: In the Data Output Hold category of the System InterfaceParameters table, changed values in the Min column for all speedsfrom 1.0 to 0. In the Electrical Characteristics table, values were addedto the System Clock Jitter row. Added Industrial temperature range of-40° C to +85° C.December 14, 2001: In Absolute Maximum Ratings Table, changedthe Industrial low-end temperature for symbol Tc to read -40 degreesinstead of 0 degrees.6 of 28 December 14, 2001
79RC64574 79RC64575Pin Description TableThe following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.Pin Name Type DescriptionSys tem InterfaceExtRqst* I External requestAn e xternal agent asserts ExtRqst* to requ est use of th e System interface . The processor grant s the requestb y asserting Release*.Rele ase* O Release interfaceIn response to the a ssert ion o f ExtRqst* or a CPU read request, the p rocessor asserts Release* and signa lsto the req uesting de vice that the syste m int erface is a vailable .RdRdy* I Read ReadyThe external a gent asserts RdRd y* to indicate that it can accept a processor read req uest .WrRdy* I Write ReadyAn e xternal agent asserts WrRdy* when it can now accept a processor write request.ValidIn* I Vali d InputSignals that an extern al age nt is now d riving a valid ad dress or data o n the SysAD bu s and a valid co mmando r data identifier on the SysCmd bus.ValidOut* O Valid OutputSignals that the processor is now driving a valid addre ss or data on the SysAD bus and a valid co mmand ord ata id entifier on the SysCmd bus.SysAD(63:0) I/O Sys tem address/data busA 64 -bit address and d ata bus for communication between the processor and an external agent. In 64 bitinterface mode, during address phases only, SysAd(35:0 ) contains invalid address in formation. The remainingSysAD(63: 36) pins are n ot used. The whole 64-bit SysAD(63 :0) may be u sed d uring the dat a transferp hase . For all dou ble-word accesse s (read or write), the low-order 3 bits (SysAD[2:0]) will always be out put aszero during the address phase.In 32-bit interfa ce mode and in the RC64574, SysAD(63:32) is not used, regard less of Endianness. A 3 2-bita ddress and data commu nication between pro cessor an d ext ernal agent is perf ormed via SysAD(31:0).SysADC(7:0) I/O Sys tem address/data check busAn 8 -bit bus co ntain ing p arity check bits for the SysAD bus during da ta bus cycles.In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contain s check bits forSysAD(31:0).SysCmd(8:0) I/O Sys tem command/data identifier busA 9-bit bus for comma nd and data identifier transmission betwee n the processor a nd an externa l age nt.SysCmdP I/O Sys tem Command ParityA single, even-parit y bit for the Syscmd bus. This signal is always d riven low.Clock/ Control InterfaceSysClock I SystemClockThe system clock input e stablish es the processo r and bu s op erating frequency. It is multiplied internally by2 ,3,4,5,6,7, or 8 to gen erate th e pip eline clock (PClock).V CCP I Quiet VCC for PLLQuiet VCC for the internal p hase locked loop.V SS P I Quiet V SS for PLLQuiet VSS for the inte rnal phase locked loop.Table 5 Pin Descriptions (Page 1 of 2)7 of 28 December 14, 2001
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