Advanced 64-bit Microprocessors Product Family 79RC64574 ...

79RC64574 79RC64575Pin Description TableThe following is a list of system interface pins available on the RC64574/575. Pin names ending with an asterisk (*) are active when low.Pin Name Type DescriptionSys tem InterfaceExtRqst* I External requestAn e xternal agent asserts ExtRqst* to requ est use of th e System interface . The processor grant s the requestb y asserting Release*.Rele ase* O Release interfaceIn response to the a ssert ion o f ExtRqst* or a CPU read request, the p rocessor asserts Release* and signa lsto the req uesting de vice that the syste m int erface is a vailable .RdRdy* I Read ReadyThe external a gent asserts RdRd y* to indicate that it can accept a processor read req uest .WrRdy* I Write ReadyAn e xternal agent asserts WrRdy* when it can now accept a processor write request.ValidIn* I Vali d InputSignals that an extern al age nt is now d riving a valid ad dress or data o n the SysAD bu s and a valid co mmando r data identifier on the SysCmd bus.ValidOut* O Valid OutputSignals that the processor is now driving a valid addre ss or data on the SysAD bus and a valid co mmand ord ata id entifier on the SysCmd bus.SysAD(63:0) I/O Sys tem address/data busA 64 -bit address and d ata bus for communication between the processor and an external agent. In 64 bitinterface mode, during address phases only, SysAd(35:0 ) contains invalid address in formation. The remainingSysAD(63: 36) pins are n ot used. The whole 64-bit SysAD(63 :0) may be u sed d uring the dat a transferp hase . For all dou ble-word accesse s (read or write), the low-order 3 bits (SysAD[2:0]) will always be out put aszero during the address phase.In 32-bit interfa ce mode and in the RC64574, SysAD(63:32) is not used, regard less of Endianness. A 3 2-bita ddress and data commu nication between pro cessor an d ext ernal agent is perf ormed via SysAD(31:0).SysADC(7:0) I/O Sys tem address/data check busAn 8 -bit bus co ntain ing p arity check bits for the SysAD bus during da ta bus cycles.In 32-bit mode and in the RC64574, SysADC(7:4) is not used. The SysADC(3:0) contain s check bits forSysAD(31:0).SysCmd(8:0) I/O Sys tem command/data identifier busA 9-bit bus for comma nd and data identifier transmission betwee n the processor a nd an externa l age nt.SysCmdP I/O Sys tem Command ParityA single, even-parit y bit for the Syscmd bus. This signal is always d riven low.Clock/ Control InterfaceSysClock I SystemClockThe system clock input e stablish es the processo r and bu s op erating frequency. It is multiplied internally by2 ,3,4,5,6,7, or 8 to gen erate th e pip eline clock (PClock).V CCP I Quiet VCC for PLLQuiet VCC for the internal p hase locked loop.V SS P I Quiet V SS for PLLQuiet VSS for the inte rnal phase locked loop.Table 5 Pin Descriptions (Page 1 of 2)7 of 28 December 14, 2001