Elektronika 2012-04 I.pdf - Instytut Systemów Elektronicznych ...

Bonding technologies for 3D-packaging(Technologie bondingu dla opakowań trójwymiarowych)Klaus-Jurgen Wolter, Karsten Meier, Peter Saettler, Iuliana Panchenko,Max FroemmigMatthias Graf Technische Universität Dresden, Electronics Packaging Laboratory, Dresden, GermanyIntroduction – State Of The Art Of SiPMarket drivers and requirements for performance pushed semiconductordevices to scaled geometries, less power, smaller sizesand lower cost. The scaling of CMOS structures “more Moore” willnot be able to meet the current and future demands of the driversdue to the functional diversification of electronics, physical limitsof CMOS technology and growth of costs.Fig. 1. System improvement by SoC or SiP solutions [1]Rys. 1. Poprawa systemu przez zastosowanie rozwiązań SoC i SiP [1]System on Chip (SoC) and System in Package (SiP) both aretechnologies which have the potential to continue the improvementin performance, size, power, and cost of electronic systems(see Fig. 1). Both technologies feature advantages and disadvantageswith respect to system integration.• SoC is a way to increase functional integration by includingsub-systems on a single chip which means large scaling butincreased design effort. For this, more than just digital functionshave to be incorporated into an integrated circuit design,e.g. analogue-to-digital and digital-to-analogue conversion.• SiP combines multiple active electronic components of differentfunctionality, assembled in a single unit. This enables multiplefunctions inserted into a system or sub-system with lowdesign effort but higher package size. A SiP may also integratepassives, MEMS, optical components and other packages. [2]The following approaches can be regarded as state of the artof SiP technologies:• Horizontal structures (Multi Chip Module as QFP, BGA or FCpackages)• Stacked structures (PoP, 3D-integration with TSVs)• Embedded structures (embedded wafer level packages(eWLP))Three-dimensional integration is an attractive way for bringingtogether various functional blocks in a vertical fashion. Hence, thereduction of package sizes leads to shorter signal and power interconnectsand results into lower signal propagation delay and powerconsumption [3]. The advances of 3D-integration can also beused for “More than Moore” approaches, where a heterogeneoussystem integration of processors, memories, sensors and actuatorsforms an interface between electronics and environment.3D-Integration Technologies3D-integration offers a new way of increasing system performanceand can be defined as any technology that stacks semiconductorelements on top of each other and utilizes vertical interconnectsElektronika 4/2012between these elements [4]. Different technologies are in use for3D-integration to design electronic systems with:• higher functionality,• smaller volume,• lower electrical parasitics between interconnects,• higher density of inter-chip interconnects• and lower high-volume manufacturing cost.3D-integration technologies can be distinguished between homogeneousand heterogeneous techniques. Integration of dieswith the same functionality is named homogeneous 3D-integrationand is used mostly for memory stacks [5]. Heterogeneous3D-integration combines dies of different functions like processors,sensors, memories and RF-components in single stack packages[6].As can be seen from roadmaps and various publications thereare numbers of 3D-integration technologies. Depending on theapplication requirements as available lateral and vertical space,I/O count, power consumption and dissipation, device speed andcost etc. packages development has been done and is still ongoing([7–9]).Focusing on moderate I/O counts, low cost, easy process implementationand high flexibility towards the combination of componentsPoP systems have been proposed. Recently, PoP systemusage grew strongly and PoPs are expected to gain more marketshare during the next years [10]. However, there are a number ofPoP varieties having differences on the first and second packagelevel.TSVs are the key feature in 3D-integration approaches basedon die stacking. The size of the TSV is substantially smaller thana wire bond or a solder bump (see Fig. 2). TSV technologies requirewafer thinning, wafer drilling, via oxidation for electrical insulationand via filling with conductive material. There are two drillingtechnologies in use, plasma drilling and laser drilling. TSVsare mainly fabricated by the Bosch process, which applies a repetitionof oxidizing the silicon via and dry etching the bottom of thevias [11]. The aspect ratio (thickness of die to diameter of via) islimited due to the limitations given by the via filling technologies.Fine-pitch vias are filled with copper or tungsten, bigger laser drilledvias can be filled with conductive paste and other materials.Fig. 2. Cross-section of TSVs for 3D-wafer level integration [12]Rys. 2. Przełom TSV dla integracji 3D na poziomie płytki [12]