HD63265 Floppy Disk Controller Users Manual 2ed Mar89 - Bitsavers

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Host(HD64180)DMAC(HD64180built-in)FDC(<strong>HD63265</strong>)1. Initialize DMAC2. Send command toFDCt1. Detect falling edgeof DMRQ2. Initiate DMAC3. Read data from memory4. Hold data in a register5. Send write data6. Set FDC allocated I/Oaddress (DACK) and WRt1. Set DREQI---,1. Reset DREQ2. Write data into a register~ ___________......JI__ --.J1. Complete transfer if DMAbyte counter becomes "0"2. Set TENDIt/DMA write cycleRepeat until all(data are transferred)t1. Detect DEND input andcomplete write operation2. Set IRQ (interrupt request)at command termination~--------------------------------------------~I1. Detect IRQ2. Read FDC resultstatusFigure 9-14.DMA Write (Memory + FDC) Sequence102 HITACHI
9.6.2 68-Series 8-Bit Bus SystemFigure 9-15 shows a typical FDC interface circuit for a HD64B180-based 68-series8-bit bus system.HD 6 4B 180 To memory circuit Address decoder <strong>HD63265</strong>(FDC)(LS138)~ __ ~A CSAo~ AI8 !Address BusAo'"'"' A7 = ) yv[)~----_---------::J---DACK1---t----aGDo~D7 (Data Bus Do~D7WRE r'I_Ao~-------------------~----------iRS: R/W logic is inverted betweenU:1PU mode and DMA mode") Do~D7vE~J~"-]---=~'"- I C~rtu1Y 11------1 R/WSelection IDMRQD-------------------------+---+---------a DREQr DENDTENDO-----~:~I=n~6~8---s-e-r-ie~s-,~H-D-6-3-26-5~'-S~I~R~Q~;----+-5--------~I-N-T 0--------'=: =P;...:l=· n=i=s:.=.;a=n=o~p=e:.=n=-=d~r=a:.=in=o::.::u=t:..;P=u=t=f~'---:::::.--=-.:=-----_-___ ~ĪRQf'RESO-----------~l---------------~-------------u RESET+5 _J
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Hitachi 8-Bit MicrocomputerHD63265F
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CONTENTSSection 1.General Descripti
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SECTION 1.GENERAL DESCRIPTION1.1 IN
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. Maximum drive control range:- Num
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SECTION 2.PIN DESCRIPTION2.1 PIN CO
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Table 2-1.TypePin FunctionsPin No.D
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RS(Register Select): RS selects the
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They must be tied to low.NC(No Conn
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Bit 4BSY (Controller Busy): Bit 4 i
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During DMA transfer, in which the F
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During polling, if the ready signal
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A: Auto precompensationWhen A = 1,
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6.2.6 ESN: End Sector NumberFigure
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6.2.12 STEP: Stepo o o o o o S T E
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HOUT: HDUT specifies the time to wa
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6.2.17 PCl, PCO: Precompensation De
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INC (Interrupt Code): INC (figure 6
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DDA (Deleted Data Address Mark): DD
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Commands other than CHECK related a
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The above commands do not activate
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READ, WRITE,COMPARE commandRead a r
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CHECK DEVICEWrite a commandparamete
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SPECIFY 1, 2corrunandwrite a corrun
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6.5 COMMAND FUNCTIONS6.5.1 READ DAT
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egister within the periods shown in
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6.5.2 READ DELETED DATABit D7 D6 D5
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CA byte does not match, only the IN
Page 57 and 58: 6.5.5 WRITE DATABi t D7 D6 D5 D4 D3
Page 59 and 60: HEX 00 is written for the remaining
Page 61 and 62: 6.5.7 WRITE FORMATBi t D7 D6 D5 D4-
Page 63 and 64: 6.5.8 SEEKBit D7 D6 D5 D4- D3 D2 Dl
Page 65 and 66: 6.5.9 RECALIBRATEBit D7 D6 D5 D4- D
Page 67 and 68: Table 6-13.Data Overrun Times8"/S"
Page 69 and 70: 6.5.11 COMPARE LOW OR EQUALBit D7 D
Page 71 and 72: 6.5.13 CHECK DEVICE STATUSBit D7 D6
Page 73 and 74: 6.5.15 SPECIFY 1Bit D7 I D6 I D5 I
Page 75 and 76: 6.5.17 SLEEPBi t D7I D6 I D5 I D4-
Page 77 and 78: 6.5.19 READ LONGBit D7 D6 D5 D4- D3
Page 79 and 80: 6.5.21 INVALIDBit D'jI D6 I Ds I DI
Page 81 and 82: 6.7 Command Code Rejection6.7.1 Phe
Page 83 and 84: Command Rejection Timing Condition
Page 85 and 86: 6.7.2 CountermeasuresHitachi recomm
Page 87 and 88: STR Check (valid for all commands e
Page 89 and 90: ABORT Command Issue (valid for all
Page 91 and 92: SECTION 7.VFO CIRCUITThe VFO circui
Page 93 and 94: Reset FDCFDC's operationReset SYNC
Page 95 and 96: SECTION 8.WRITE PRECOMPENSATION CIR
Page 97 and 98: 9.2 SYSTEM OPERATION SEQUENCEFigure
Page 99 and 100: 9.3.2 WRITE OperationFigure 9-4 sho
Page 101 and 102: Table 9-1.FDC Data Transfer Timing8
Page 103 and 104: 9.5 FDC CONTROL9.5.1 FDC Operating
Page 105 and 106: CSRS (Ao )RDWRDATAtAH(min)PVVimL On
Page 107: Since the DACK signal of the FDC ca
Page 111 and 112: R/W, CS and RS are sampled at the r
Page 113 and 114: Table 9-3Data Transfer Rate Selecti
Page 115 and 116: HD63265 (FDC)WDATA~----------------
Page 117 and 118: Table 9-5.8" FDD Interface Signals
Page 119 and 120: Table 9-7.3.5" FDD Interface Signal
Page 121 and 122: 10.3 ELECTRICAL CHARACTERISTICS10.3
Page 123 and 124: AC Specification (cant)No. Item Sym
Page 125 and 126: ~ReadcycleWritecycleRS,C S00-07(out
Page 127 and 128: @tususa. US1. HDIRtupSTEPFigure 10-
Page 129 and 130: 5.0V2.4 kQIS2074 ®All diodesare 1S
Page 131 and 132: HD63265 User's ManualPublication Da
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HD63265 Floppy Disk Controller Users Manual 2ed Mar89 - Bitsavers

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