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muons 2 or two PSB channels (named CA1-CA10 from Table 5.1 for the inputs fromGMT and MU1MU2 and MU3MU4 for the two muon pairs from the GMT). Theresulting algorithm bits are read out from an FDL spy memory.The patterns are designed to highlight common electronics problems:• “Running zero” test: sets all input bits but one in each 16 bit input word.• “Running one” test: clears all input bits but one in each 16 bit input word.• “Counter” test: run all bytes of the input through sequences from 0 to 255.• “Inversion” test: performs inversion of subgroups from 1 to 32 bits, which isespecially sensitive to problems in the power supply of the tested components.• “Random number” test: complements the pre-defined patterns, in the hope ofrevealing anomalies missed through the more systematic tests.Each input is distributed to both of the COND chips, but since only 128 of the 192output bits of the GTL reach the FDL, only the lower 32 bits of the output from theCOND1 chip can be examined. Comparing the output to the expected input thenyields the result. Thus, the result of a full interconnection test is organized in a twolevelhierarchy according to the input tested and the pattern used. For each of theseparameters, it produces a list of mismatches between input values and results.Interpretation of ResultsThe detailed routing of signals on the GTL board is shown in Fig. 5.3. Each input isrouted over the backplane to exactly one of the three receiver chips (see Table 5.3).This layout implies the following conditions that are helpful for analysis of bit errors:• Errors common to all input particles are likely caused by either the COND chipsor the signal routing to the FDL.• Static errors between the input simulation and the REC chip appear in triplicate:they affect both lines deserialized from a single 80 MHz line, which are againduplicated to two COND chips, and one of the four instances is truncated becauseonly 32 bits from COND1 are sent to the FDL.• In contrast, errors between the REC and COND chips will manifest only onceper COND chip.These criteria could in principle be used for automated diagnosis of these errormodes, but the added complexity did not appear to be justified because the additionalinformation does not help non-experts to deal with the problems and experts preferto be confronted with a unified view of errors for arbitrarily complex failure mode.2 Contrary to the function tests, the GMT is not included in these tests because it lacks a similarbypass mode and the more repetitive manner of the bit patterns negates the disadvantage of theshort simulation memory.59
Receiver ChipREC1REC2REC3Logical InputMU1MU2MU2MU3CA1CA2CA3CA4CA5CA6CA7CA8CA9CA10Table 5.3: Assignment of logical GTL inputs to receiver chips.80 MHz 40 MHzPSB or GMT via backplane32 linesRECnCOND164 lines to eachCOND232 lines96 linesFDLFigure 5.3: Schematic of GTL connections exercised during the interconnection test.60
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factor. The selected events are the
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