Test Cost

Test Cost 절감을 위한Test Item 선정LG전자전준우책임연구원LG Electronics 2008

Purpose• Test Cost는 회사 이익에 중요한 역할을 하는 것으로서 품질과 신뢰성을 보장하는 범위에서 test cost reduction 작업은 이루어져야 한다.• 이를 위해서는 test setup 안정화와 함께 test timereduction (TTR)이 이루어 져야 한다.• 본 자료에서는 대상 device에서 진행한 test setup 안정화와 TTR을 위해 적용된 내용 기술 및 양산 data를 통해서분석 및 적용한 결과를 기술하였다.

Outline• ASIC device test setup flow• Test cost reduction• TEST에서의 Test Cost Reduction Methods• 설계에서의 Test Cost Reduction Methods

ASIC device test setup flow• General device test setup flowProbe CardSimulation (*1)Probe Card 제작Wafer TestDesignFab양산FT boardSimulation (*1)FT board 제작FT setup*1: for high speed device*2: SLT (system level test) 추가 진행

Test cost reduction• Quality and Reliability를 유지한 상태에서 test cost를줄이는 모든 방법으로서 design에서부터 양산monitoring까지 모두 고려 되어야 한다Figure. Cost of silicon manufacturing and testFigure. Cost of test challenge (verigy.com)

Test cost reduction• Test setup 안정화– 설계에서의 test setup 안정화– Test에서의 test setup 안정화• Test time reduction (TTR)– 설계에서의 TTR– Test에서의 TTR

적용 device• ASIC1– 0.13um Digital to Analog converter SoC– ARM9 embedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 1ch-DAC– 256PBGA• ASIC2– 65nm Digital to Analog converter SoC of 5M gates– ARM9 embedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 3ch-DAC– 256PBGAFigure. ASIC2 block diaram

Test에서의 test cost reduction• Quality & reliability를 만족하는 test setup• Test setup의 안정화– IDD등 test item 안정화를 위한 H/W, S/W 대응• Test에서의 TCR– Test house 선정시 ATE 단가– Test time reduction (TTR)– ATE별최대가능multi-site test– ATE별 test item별로 parallel test시 TTR 영향 고려– Concurrent test– 양산 & 불량율 monitoring을 통한test item 최적화 및 재배치– Wafer test item versus package test item 최적화– Vector truncation– Vector elimination– Architectural methods– Test program optimization– 높은 first yield 유지– Adaptive test flow– Low cost ATE 활용

Vector truncation (Maxwell 2006)• 10% of the vector => 96% of failures• 10% of the AC scan vector => 62% of failures• Wafer test vector truncation• Package yield dropFigure. Cumulative fallout of stuck-at scan vectorsFigure. Cumulative fallout of AC scan vectors

Vector elimination (Maxwell, 2007)• ATPG tool generates patterns using an abstract model with noknowledge of the defect detection capability of the resultanttests• In reality, there are large differences in the effectiveness ofeach pattern• The three most effective tests detects 35 of the 41 failures, theremaining i contributing ti only 60 DPMFigure. Number of fails for each test

Multi-site test• ATE별로 device에 적용가능한최대multi-site수가 다름• 고가의 ATE 적용시 최대 multi-site수와 저가의 ATE에 적용시 최대 multi-site 수를 고려하여 COT를를 비교• Multi-site수를 늘리기 위해 design에서 pin count를 줄임• ATE specifation을 넘어선 경우에는 application을 통해대응– Channel 부족 : Photo-MOS relay사용– Analog channel 부족:

Concurrent test• Tests are run in parallel within the same device• Major savings can be expected (rivoir, 2004)• Design have to be added for this modeSRAMFUNCPLLADCDACSRAMFUNCPLLADCDACFigure. Conventional testFigure. Concurrent test

Test order (Butler & Saxena,2000)• Reordering tests to put the most time-effective firstin the flow• On one study, it showed an 8% decrease in test time• This method does not apply to fabless company

Low cost ATE• Digital part에 대해서는 우수한 비용 절감• Analog part 및 debugging 관련해서는 성능 저하• ATE별별 여러 제한 사항에 따라 TTR의의 효과가 다름• High speed interface에서 loop back testFigure. DVI loop back test load boardFigure. DUT vs ATE trend

Wafer test vs package test• Package test는 최종단으로 full test 적용• Vector truncation at wafer test• Wafer test에서 yield 분석으로 일부의 test item만 적용• wafer test에서 low speed test를 적용• Wafer test에서 저가의 ATE를 사용• Wafer test t yield가 높은 경우 wafer test t skip을 을 고려• FT yield drop에 따른package 손실 비용 고려

Special package tests (maxwell, 2007)• Package test had to be repeated even though the diehad been prescreened on wafer test (maxwell, 2002)• Peripheral vector vs normal vector– Faults in the pad and pad logic– Faults in “logical proximity” to pad– Faults in physical proximity it to pad• The periphery set are not a satisfactory replacementFail regular scan physical logicalStuck-at 641msTransition 710msStuck-at physical 20msTransition physical 58msStuck-at logical 12msTransition logical 25msStuck-at pad 10msTransition pad 18msTable. Execution times of tests2336 2 0 10Fail peripherypad110 0Figure. Distribution of failed parts0

Voltage stress test• Reliability Screening• Test time & Test pattern & Test voltage• Foundry dependent• Stuck-at SCAN, MBIST• Outlier screenig• 0.01% yield reduction (Maxwell, 2007)• Pre & Post screening

Analog test time reduction• ADC & DAC TTR– AC, DC test item의 선정– Sample 수의 감소– Bit수의 감소– Stabilization time의 단축• PLL TTR– 중복되는 test item의 제거– Data 산포에 영향을 주지 않는 Sampling 수의 선정– Loop-back test를 통한여러pll의 동시test1.41.21TestTime v s Sample CountTimeTest T0.80.60.40.2010002000300040005000600070008000900010000110001200013000Sample count14000150001600017000180001900020000SPLL(175Mhz) FS(27Mhz) AuPLL(24Mhz) DPLL(27.1Mhz)Figure. Test time vs sample count in PLL test

Adaptive test flow (Madge et al., 2005)• In a variation of some techniques described , asample of die can be tested with a complete test, anddepending on the yield, remaining die can be testedwith a reduced d set• From a TTR perspective, a die surrounded by gooddie can be adequately tested with a reduced test setcompared to one which is in a bad neighborhood

기타• Eliminating redundant voltage coners• ATE 단가 (for fabless company)• Test program optimization• 높은 first yield 유지• Test frequency speed up• Test setup 안정화 (재현성 확보)• Removing redundant test items

설계에서의 test cost reduction• 충분한 설계 마진을 갖는 device를 설계• 설계에서의 안정화– SI/ PI board simulation (high speed device)– 설계 안정화 (floating node 제거 등)– IDD 산포 안정화를 위한 설계 변경 및 벡터 대응• 설계에서의 TCR– DFT의강화(Scan compression, At-speed MBIST with PLL)– Fault model ( stuck-at, t small delay transition, path delay, bridging i )– Concurrent Test Design– Loop-back test– MCP test mode 고려

SI/PI Simulation setup condition• DDR Interface sim. Signal/Power Integrity with SSN– I/O interface• Operating Frequency : 175 MHz• CLK/CLKB/DQ#/DM#/DQS#/Addr./Ctrl. /Ct • Signal driving IBIS model / Signal receiving load C– Write mode» 16bit data/Clk/Clk_B/DQS signals simultaneousswitching– Control mode» Address /Control signals– Power ripple check• +2.5v main• +1.25v reference• Rs damping resistor value tuning• Rs = 22 ohm• Rs = 15 ohm

SI/PI Simulation setup condition• Package + FT Board– Pkg. 4 layer– FT Board 24 layerInput Pogo probingRs Damping ResistorDie pad Signal output

SI/PI Simulation analysis target• Power Integrity 검증– Pogo 단에서 2.5v power 인가 후, DUT에서 signal transient 에 의한power ripple 관찰• Power plane 의 impedance resonance 확인– Ground Bounce 에 의한1.25v Vref. ripple 관찰• Signal Integrity 검증– Trace/via/pad/Rs 의 discontinued impedance 에 의한reflection 관찰• DDR 의 Electrical spec. 만족여부 확인• Undershoot/overshoot– Trace length 차이에 의한 skew 검증• CLK/DQS/DQ/DM 간의 timing margin확인• Test 장비에서 delay/skew 보정을 위한 정보 제공– Cross-talk 에의한distortion 확인– Signal driving 시 power 공급이 원활한지 check

SI/PI Simulation DDR write mode2.5V powerDQ#/DMDQS#•ASIC2 에서 출력된 신호가 slot 의 pogo에서 입력받는 파형을 추출한 결과•Site1/2 가 동시에 data write mode 로 동작시, 악조건으로 시뮬레이션한 결과임• Site1/2 사이 DQ# 및 DM 간 delay 는148ps 로양호CLK Diff. probingRs=22ohmVref. 1.25v1.25vDQ#/DM 간 delay 차 = 약 148psRs=15ohm margin 이 높음• Clk/ClkB 의 single ended probing 결과는2.5v power ripple 의 영향으로 좋지 않으나, differential probing 의 결과가 양호하기 때문에 동작상 문제없음.

SI/PI Simulation DDR addr/ctrl modeAddr./Ctrl.•ASIC2 에서 출력된 신호가 slot 의 pogo에서 입력받는 파형을 추출한 결과•Site1/2 가 동시에 Addr./Ctrl. Signal 들이switching 함.• Site1/2 사이 Addr.# 및 Ctrl. 간 delay 는169ps 로양호CLK Diff. probingRs=22ohm1.25vRs=15ohm margin 이 높음Addr.#/Ctrl. 간 delay 차 = 약 169ps

Design for test• Test quality, test time reduction

Fault models• Stuck-at fault– A line has a stuck-at fault if it has a fixed logic value regardlessof the change in input values of a circuit• Bridging fault– Two or more lines that are normally independent d becomeconnected when faulty• Delay fault– Transition fault– Path delay fault

Scan stitching• Scan Test– Scan test t divides id chip operations into two mode, which h are shift and capture.– Shift mode : test patterns are applied or observed through scan chains whichconnect flip-flops serially.– Capture mode : data evaluated by combinational logics at normal operationmode are latched to scan flip-flop.

Scan stitching• Scan Compression– Architectured2a1T16 16test_si192 192data_in data_out data_in data_outtest_soSCCOMP_DECOMPRESSORselscan chainSCCOMP_COMPRESSORSTPI_VALIDSTPI_SOPSTPI_DATASTPI_CLKGPIO[0]TMOD_Ntest modedecoding logic– Advantagetest_setwhen TMOD_N = 0, {GPIO[0], STPI_CLK, STPI_DATA} = 3’b111test_se = STPI_VALIDad_scan_mode = STPI_SOP ( 1 : ScanCompression_mode,**0 : Internal_scan)• Decrease test time and test data volume• Increase test quality when addressed ATE memory limitation problem– Disadvantage• Area overhead : 10 gates per 1 sub scan chain– Compression ratio : 10X

Scan flow (stuck-at test)• Test Sequence– Test setup– Shift– Hold– Force PI– Measure PO– Capture– Reshift & Measure scan out

At-speed test• Capture timing diagramshiftlaunch capture shift

At-speed test• ATPG will target both Small Delay Defect (SDD) target faults andnon-target t faults– Uses slack-based test generation for defined SDD target faults– Uses regular transition fault test generation for all others in fault list• Slack-aware tests detect small-delay defects– ATPG selects observation path with lowest slack– Slack data from Prime Time

ASIC2 floor plan2.6V SSTL2 I/O * Physical mapMemory : 26%AIP : 12%Logic : 62%3.3V digital3.3V digitalAIP62.5V1.2VESD dummyESD dummyAIP1AIP2AIP3AIP4AIP52.5V 1.2V 2.5V 1.2V 1.2V 1.2V digital, 1.2V analog, 3.3V digital2.5V analogPower Cut Cell(PRCUTA or PRCUT)

ASIC2 fault summary (Probe test)O/S P/S IIL IPU IIL SIDD AIDD MBIST SCAN SC_TR SC_PATH SC_BRPer fail1.602% 9.766% 0.689% 0.000% 0.576% 9.496% 0.811% 30.427% 38.571% 8.031% 0.020% 0.012%* path delay pattern is covered 10ppm in wafer test and 132ppm in package test* Bridging pattern is covered 5~6ppm in wafer test and 5ppm in package test*sample is more than 6MTotal faults 90%(excluded AIP, DDR interface) Undetected fault : 10%(AIP, DDR interface)IIL, IPU, SIDD, AIDD, O/S, P/S20.7%Transition7.2%Stuck-at35%MBIST27.1%Included PLLPath delay0.02%Bridging0.012%

BIST clock, controller & collar

적용 결과• ASIC1은 low cost ATE에서 ASIC2는 high cost ATE에서 setup• 각각 현 device에서 최대 적용가능한 multi site수를 적용• FT TTR 적용 결과– 16.19% 19% TTRFigure. TTR 적용 결과 (Low cost ATE)

적용 결과• FT Multi-site & TTR & ATE별 적용결과– 19.3% TTR, +4.8% 증가Figure. Low cost ATE vs high cost ATEFigure. Multi site 적용 결과