Test Cost

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Low cost ATE• Digital part에 대해서는 우수한 비용 절감• Analog part 및 debugging 관련해서는 성능 저하• ATE별별 여러 제한 사항에 따라 TTR의의 효과가 다름• High speed interface에서 loop back testFigure. DVI loop back test load boardFigure. DUT vs ATE trend
Wafer test vs package test• Package test는 최종단으로 full test 적용• Vector truncation at wafer test• Wafer test에서 yield 분석으로 일부의 test item만 적용• wafer test에서 low speed test를 적용• Wafer test에서 저가의 ATE를 사용• Wafer test t yield가 높은 경우 wafer test t skip을 을 고려• FT yield drop에 따른package 손실 비용 고려
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5 and 6: Test cost reduction• Quality and
Page 7 and 8: 적용 device• ASIC1- 0.13um Digi
Page 9 and 10: Vector truncation (Maxwell 2006)•
Page 11 and 12: Multi-site test• ATE별로 device
Page 13: Test order (Butler & Saxena,2000)
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21 and 22: 설계에서의 test cost reduction
Page 23 and 24: SI/PI Simulation setup condition•
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27 and 28: Design for test• Test quality, te
Page 29 and 30: Scan stitching• Scan Test- Scan t
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33 and 34: At-speed test• ATPG will target b
Page 35 and 36: ASIC2 fault summary (Probe test)O/S
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

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