Test Cost

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Fault models• Stuck-at fault– A line has a stuck-at fault if it has a fixed logic value regardlessof the change in input values of a circuit• Bridging fault– Two or more lines that are normally independent d becomeconnected when faulty• Delay fault– Transition fault– Path delay fault
Scan stitching• Scan <strong>Test</strong>– Scan test t divides id chip operations into two mode, which h are shift and capture.– Shift mode : test patterns are applied or observed through scan chains whichconnect flip-flops serially.– Capture mode : data evaluated by combinational logics at normal operationmode are latched to scan flip-flop.
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5 and 6: Test cost reduction• Quality and
Page 7 and 8: 적용 device• ASIC1- 0.13um Digi
Page 9 and 10: Vector truncation (Maxwell 2006)•
Page 11 and 12: Multi-site test• ATE별로 device
Page 13 and 14: Test order (Butler & Saxena,2000)
Page 15 and 16: Wafer test vs package test• Packa
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21 and 22: 설계에서의 test cost reduction
Page 23 and 24: SI/PI Simulation setup condition•
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27: Design for test• Test quality, te
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33 and 34: At-speed test• ATPG will target b
Page 35 and 36: ASIC2 fault summary (Probe test)O/S
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

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