Test Cost

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ASIC2 floor plan2.6V SSTL2 I/O * Physical mapMemory : 26%AIP : 12%Logic : 62%3.3V digital3.3V digitalAIP62.5V1.2VESD dummyESD dummyAIP1AIP2AIP3AIP4AIP52.5V 1.2V 2.5V 1.2V 1.2V 1.2V digital, 1.2V analog, 3.3V digital2.5V analogPower Cut Cell(PRCUTA or PRCUT)
ASIC2 fault summary (Probe test)O/S P/S IIL IPU IIL SIDD AIDD MBIST SCAN SC_TR SC_PATH SC_BRPer fail1.602% 9.766% 0.689% 0.000% 0.576% 9.496% 0.811% 30.427% 38.571% 8.031% 0.020% 0.012%* path delay pattern is covered 10ppm in wafer test and 132ppm in package test* Bridging pattern is covered 5~6ppm in wafer test and 5ppm in package test*sample is more than 6MTotal faults 90%(excluded AIP, DDR interface) Undetected fault : 10%(AIP, DDR interface)IIL, IPU, SIDD, AIDD, O/S, P/S20.7%Transition7.2%Stuck-at35%MBIST27.1%Included PLLPath delay0.02%Bridging0.012%
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5 and 6: Test cost reduction• Quality and
Page 7 and 8: 적용 device• ASIC1- 0.13um Digi
Page 9 and 10: Vector truncation (Maxwell 2006)•
Page 11 and 12: Multi-site test• ATE별로 device
Page 13 and 14: Test order (Butler & Saxena,2000)
Page 15 and 16: Wafer test vs package test• Packa
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21 and 22: 설계에서의 test cost reduction
Page 23 and 24: SI/PI Simulation setup condition•
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27 and 28: Design for test• Test quality, te
Page 29 and 30: Scan stitching• Scan Test- Scan t
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33: At-speed test• ATPG will target b
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

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