Test Cost

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Test cost reduction• Test setup 안정화– 설계에서의 test setup 안정화– Test에서의 test setup 안정화• Test time reduction (TTR)– 설계에서의 TTR– Test에서의 TTR
적용 device• ASIC1– 0.13um Digital to Analog converter SoC– ARM9 embedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 1ch-DAC– 256PBGA• ASIC2– 65nm Digital to Analog converter SoC of 5M gates– ARM9 embedded– 16b DDR1 I/F @ 175Mhz– PLL 4종, 10bit ADC, 10bit 3ch-DAC– 256PBGAFigure. ASIC2 block diaram
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5: Test cost reduction• Quality and
Page 9 and 10: Vector truncation (Maxwell 2006)•
Page 11 and 12: Multi-site test• ATE별로 device
Page 13 and 14: Test order (Butler & Saxena,2000)
Page 15 and 16: Wafer test vs package test• Packa
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21 and 22: 설계에서의 test cost reduction
Page 23 and 24: SI/PI Simulation setup condition•
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27 and 28: Design for test• Test quality, te
Page 29 and 30: Scan stitching• Scan Test- Scan t
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33 and 34: At-speed test• ATPG will target b
Page 35 and 36: ASIC2 fault summary (Probe test)O/S
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

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