Test Cost

More documents

Recommendations

Info

SI/PI Simulation setup condition• DDR Interface sim. Signal/Power Integrity with SSN– I/O interface• Operating Frequency : 175 MHz• CLK/CLKB/DQ#/DM#/DQS#/Addr./Ctrl. /Ct • Signal driving IBIS model / Signal receiving load C– Write mode» 16bit data/Clk/Clk_B/DQS signals simultaneousswitching– Control mode» Address /Control signals– Power ripple check• +2.5v main• +1.25v reference• Rs damping resistor value tuning• Rs = 22 ohm• Rs = 15 ohm
SI/PI Simulation setup condition• Package + FT Board– Pkg. 4 layer– FT Board 24 layerInput Pogo probingRs Damping ResistorDie pad Signal output
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5 and 6: Test cost reduction• Quality and
Page 7 and 8: 적용 device• ASIC1- 0.13um Digi
Page 9 and 10: Vector truncation (Maxwell 2006)•
Page 11 and 12: Multi-site test• ATE별로 device
Page 13 and 14: Test order (Butler & Saxena,2000)
Page 15 and 16: Wafer test vs package test• Packa
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21: 설계에서의 test cost reduction
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27 and 28: Design for test• Test quality, te
Page 29 and 30: Scan stitching• Scan Test- Scan t
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33 and 34: At-speed test• ATPG will target b
Page 35 and 36: ASIC2 fault summary (Probe test)O/S
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?