Test Cost

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Vector elimination (Maxwell, 2007)• ATPG tool generates patterns using an abstract model with noknowledge of the defect detection capability of the resultanttests• In reality, there are large differences in the effectiveness ofeach pattern• The three most effective tests detects 35 of the 41 failures, theremaining i contributing ti only 60 DPMFigure. Number of fails for each test
Multi-site test• ATE별로 device에 적용가능한최대multi-site수가 다름• 고가의 ATE 적용시 최대 multi-site수와 저가의 ATE에 적용시 최대 multi-site 수를 고려하여 COT를를 비교• Multi-site수를 늘리기 위해 design에서 pin count를 줄임• ATE specifation을 넘어선 경우에는 application을 통해대응– Channel 부족 : Photo-MOS relay사용– Analog channel 부족:
Page 1 and 2: Test Cost 절감을 위한Test Item
Page 3 and 4: Outline• ASIC device test setup f
Page 5 and 6: Test cost reduction• Quality and
Page 7 and 8: 적용 device• ASIC1- 0.13um Digi
Page 9: Vector truncation (Maxwell 2006)•
Page 13 and 14: Test order (Butler & Saxena,2000)
Page 15 and 16: Wafer test vs package test• Packa
Page 17 and 18: Voltage stress test• Reliability
Page 19 and 20: Adaptive test flow (Madge et al., 2
Page 21 and 22: 설계에서의 test cost reduction
Page 23 and 24: SI/PI Simulation setup condition•
Page 25 and 26: SI/PI Simulation DDR write mode2.5V
Page 27 and 28: Design for test• Test quality, te
Page 29 and 30: Scan stitching• Scan Test- Scan t
Page 31 and 32: Scan flow (stuck-at test)• Test S
Page 33 and 34: At-speed test• ATPG will target b
Page 35 and 36: ASIC2 fault summary (Probe test)O/S
Page 38 and 39: 적용 결과• ASIC1은 low cost

Test Cost

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