Texas Instruments TPS65020 Power Management IC - Toradex

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TPS65020SLVS607C –SEPTEMBER 2005–REVISED SEPTEMBER 2011www.ti.comNAMETERMINALNO.I/OTERMINAL FUNCTIONS (continued)DESCRIPTIONPower supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.VCC 37 I This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.Also supplies serial interface blockInput signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V This pin can also be connected toDEFDCDC1 10 I a resistor divider between VDCDC1 and GND. If the output voltage of the DCDC1 converter is set ina range from 0.6 V to VINDCDC1 VInput signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 2.5 V This pin can also be connectedDEFDCDC2 32 I to a resistor divider between VDCDC2 and GND. If the output voltage of the DCDC2 converter is setin a range from 0.6 V to VINDCDC2 VInput signal indicating default VDCDC3 voltage, 0 = 1.3 V, 1 = 1.55 V This pin can also be connectedDEFDCDC3 1 I to a resistor divider between VDCDC3 and GND. If the output voltage of the DCDC3 converter is setin a range from 0.6 V to VINDCDC3 VDCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.LDO REGULATOR SECTIONVINLDO 19 I I Input voltage for LDO1 and LDO2VLDO1 20 O Output voltage of LDO1VLDO2 18 O Output voltage of LDO2LDO_EN 22 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOsVBACKUP 15 I Connect the backup battery to this input pin.VRTC 16 O Output voltage of the LDO/switch for the real time clockVSYSIN 14 I Input of system voltage for VRTC switchCONTROL AND I 2 C SECTIONHOT_RESET 11 I Push button input used to reboot or wake-up processor via RESPWRON output pinTRESPWRON 26 I Connect the timing capacitor to this pin to set the reset delay time: 1 nF → 100 msRESPWRON 27 O Open drain System reset outputPWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.LOW_BAT 21 O Open drain output of LOW_BAT comparatorINT 28 O Open drain outputSCLK 30 I Serial interface clock lineSDAT 29 I/O Serial interface data/addressPWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL outputLOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT outputPB_IN 12 I/O Push button input debounced and output fed to latch at PB_OUTPB_OUT 13 I/O Open drain output of latch driven by PB_IN. Low after power up.12 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments IncorporatedProduct Folder Link(s) : TPS65020
TPS65020www.ti.com SLVS607C –SEPTEMBER 2005–REVISED SEPTEMBER 2011FUNCTIONAL BLOCK DIAGRAMVSYSINVCCTHERMALSHUTDOWNVBACKUPVRTCBBATSWITCHVINDCDC1SCLKSDATSerial InterfaceDCDC1STEP-DOWNCONVER TERL1VDCDC1DEFDCDC1PGND1DCDC1_ENDCDC2_ENDCDC3_ENLDO_ENHOT_RESETCONTROLDCDC2STEP-DOWNCONVERTERVINDCDC2L2VDCDC2DEFDCDC2PGND2RESPWRONVCCINTAGND1VINDCDC3LOWBAT_SNSPWRFAIL_SNSLOW_BATTPWRFAILTRESPWRONUVLOVREFOSCDCDC3STEP-DOWNCONVERTERL3VDCDC3DEFDCDC3PGND3PB_INInput bufferJK-flipflopVLDO1VLDO1PB_OUT200-mA LDOAGND2VINLDOVLDO2200-mA LDOVLDO2Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 13Product Folder Link(s) : TPS65020
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Texas Instruments TPS65020 Power Management IC - Toradex

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