Texas Instruments TPS65020 Power Management IC - Toradex

TPS65020SLVS607C –SEPTEMBER 2005–REVISED SEPTEMBER 2011www.ti.comAPPLICATION INFORMATIONLayout ConsiderationsAs for all switching power supplies, the layout is an important step in the design. Proper function of the devicedemands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. Ifthe layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues aswell as EMI problems. It is critical to provide a low impedance ground path. Therefore, use wide and short tracesfor the main current paths. The input capacitors should be placed as close as possible to the IC pins as well asthe inductor and output capacitor.For TPS65020, connect the PGND pins of the device to the PowerPAD land of the PCB and connect theanalog ground connections (AGND) to the PGND at the PowerPAD. It is essential to provide a good thermaland electrical connection of all GND pins using multiple vias to the GND-plane. Keep the common path to theAGND pins, which returns the small signal components, and the high current of the output capacitors as short aspossible to avoid ground noise. The VDCDCx line should be connected right to the output capacitor and routedaway from noisy components and traces (for example, the L1, L2 and L3 traces).Input Voltage ConnectionThe low power section of the control circuit for the step-down converters DCDC1, DCDC2 and DCDC3 issupplied by the Vcc pin while the circuitry with high power such as the power stage is powered from theVINDCDC1, VINDCDC2 and VINDCDC3 pins. For proper operation of the step-down converters, VINDCDC1,VINDCDC2,VNDCDC3 and Vcc need to be tied to the same voltage rail. Step-down converters that are plannnedto be not used, still need to be powered from their input pin on the same rails than the other step-downconverters and Vcc.LDO1 and LDO2 share a supply voltage pin which can be powered from the Vcc rails or from a voltage lowerthan Vcc e.g. the output of one of the step-down converters as long as it is operated within the input voltagerange of the LDOs. If both LDOs are not used, the VINLDO pin can be tied to GND.Requirements for Supply Voltages below 3.0VFor a supply voltage on pins Vcc, VINDCDC1, VINDCDC2 and VINDCDC3 below 3.0V, it is recommended toenable the DCDC1, DCDC2 and DCDC3 converters in sequence. If all 3 step-down converters are enabled atthe same time while the supply voltage is close to the internal reset detection threshold, a reset may begenerated during power-up. Therefore it is recommended to enable the dcdc convertes in sequence. This can bedone by driving one or two of the enable pins with a RC delay or by driving the enable pin by the output voltageof one of the other step-down converters. If a voltage above 3.0V is applied on pin VBACKUP while Vcc andVINDCDCx is below 3.0V, there is no restriction in the power-up sequencing as VBACKUP will be used to powerthe internal circuitry.Unused RegulatorsIn case a step-down converter is not used, its input supply voltage pin VINDCDCx still needs to be connected tothe Vcc rail along with supply input of the other step-down converters. It is recommended to close the controlloop such that an inductor and output capacitor is added in the same way as it would be when operatednormally. If one of the LDOs is not used, its output capacitor should be added as well. If both LDOs are not used,the input supply pin as well as the output pins of the LDOs (VINLDO, VLDO1, VLDO2) should be tied to GND.IMPLEMENTING A PUSH-BUTTON ON-OFF FUNCTION USING PB_IN AND PB_OUTIn mobile phone applications, the device must not automatically power up when the battery is inserted. UsingPB_IN and PB_OUT prevents power up. After the main battery is inserted, the PB_OUT open drain output is low.When this pins is connected with PWRFAIL, the signal is pulled low, preventing the Intel® PXA270 start up.See the latest version of Intels technical specifications about the Intel® PXA270 Processor Family for additionalinformation on the functionality of this chip and possible limitations.42 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments IncorporatedProduct Folder Link(s) : TPS65020