Wireless Intel SpeedStep Power Manager

White PaperWireless Intel SpeedStep ® Power ManagerRead PMUEventsCalculatethe StatisticDeterminethe StateInterfacewith PMPower Manager Idle ProfilerFigure 9. Performance ProfilerThe PMU tracks processor events as described in Table 2. ThePerformance Profiler also monitors the status registers ofperipheral devices such as the Intel PXA27x processor’s LCDController. This monitoring allows the Performance Profiler todynamically characterize the system state.8.0 Policy ManagerThe Policy Manager defines power states and maps them topower modes of the Intel PXA27x processor and/or WirelessIntel Communications Processor. If a power state is native tothe operating system, the Policy Manager uses the nativepower state and the operating system’s interface to the DPIsto transition the system into the specified power state. If thepower state is not native to the operating system, the PolicyManager creates the power state and uses the DPIs totransition the system into the specified power state.The Policy Manager uses device driver inputs, applicationworkload inputs (optional), Idle Profiler inputs, and PerformanceProfiler (system workload) inputs to define the system’s powerpolicy. Alternatively, an OEM can use these inputs to define itsown power policy.The Power Manager software provides an infrastructure to thedevice drivers for state changes, frequency changes, and voltagechanges. Using this infrastructure, the Power Manager softwarenotifies the client drivers of these changes either directly orthrough the operating system’s power management services.A system that is enabled by the Power Manager software willalways maintain a predefined operating point as part of a globalvariable, namely IPMOperatingPoint = [State, Voltage, Frequency,Frequency2, Frequency3]Information SourcePMU RegistersDescription of EventInstruction cache-missInstruction cache cannot deliverinstructionData dependency stallInstruction TLB missData TLB missInstruction executedNumber of Stalls an number of times thestall occurs due to D-Cache buffer full(every cycle condition is present)Data cache accessData cache-missData cache write-backSoftware changed the PCUsage for CharacterizationInstruction traffic and CPI estimation andcache locality%Memory usePage locality%CPU UsedData traffic / Data access congestion /Congestion rate and congestion lengthsData access rate, memory bound,%Memory useData traffic and %Memory useData trafficNumber of function callsTable 2. Intel ® PXA27x Processor’s Performance Monitoring Unit (PMU)12