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Wireless Intel SpeedStep Power Manager

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<strong>Wireless</strong> <strong>Intel</strong> <strong>SpeedStep</strong> ® <strong>Power</strong> <strong>Manager</strong>White Paper1. The <strong>Power</strong> <strong>Manager</strong> software notifies the communicationsdriver of the need to transition the communicationssubsystem into the Standby power state.2. The communications driver sends a “change to Standby powerstate” message over the <strong>Intel</strong> MSL to the communications powermanagement component of the communications subsystem.3. The communications subsystem enters the Standby powerstate and prepares itself to wake-up the applications subsystemif the communications subsystem transitions into a newstate that requires processing in the applications subsystem.Similarly, for dynamic performance and power scaling, thecommunications device driver is notified about a frequencyand voltage change, and in turn notifies the communicationssoftware of such via the <strong>Intel</strong> MSL.4.0 <strong>Intel</strong> ® PXA27x—Low <strong>Power</strong>EnhancementsThe <strong>Intel</strong> PXA27x processor implements <strong>Wireless</strong> <strong>Intel</strong><strong>SpeedStep</strong> ® Technology in hardware by providing the following:4.1 Reset Sources■■■■■■<strong>Power</strong>-on ResetHardware ResetWatchdog Timer ResetGPIO ResetReset on exit from Sleep modeReset on exit from Deep-Sleep mode4.2 Clock Gating for PeripheralsThe <strong>Intel</strong> PXA27x processor not only allows each of itsperipherals to be independently enabled or disabled, it alsoallows the clock to each peripheral to be independently gatedon or off.4.3 <strong>Power</strong> Modes■■■■Deep Idle mode: This mode can be entered only after thecore frequency has been changed to 13 MHz. Clocks to theCPU are disabled; recovery is through interrupt assertion.Standby mode: All internal power domains except VCC_RTCand VCC_OSC are placed in a low-power mode where stateis retained but no activity is allowed. The clock sources maybe disabled. Some of the internal power domains can bepowered off, and both PLLs are disabled. Recovery is throughexternal and selected internal wake-up events.Sleep mode: All internal power domains except VCC_RTCand VCC_OSC (both are internal supplies) can be poweredoff. All clock sources, except those used by the real-timeclock (RTC) and the power manager unit, are disabled. The<strong>Intel</strong> PXA27x processor’s PWR_EN output pin de-asserts tooptionally disable the external low-voltage power supplies tothe <strong>Intel</strong> PXA27x processor's low-voltage domains. Theremaining power domains are placed in a low-power statewhere state is retained but no activity is allowed. Recoveryis through external and selected internal wake-up events.Because the program counter is invalid, recovery requires asystem reboot (the program counter restarts from 0x0, sothe core begins execution starting at the reset vector).Deep Sleep mode: All internal power domains exceptVCC_RTC and VCC_OSC can be powered off. All clocksources, except those used by the RTC and the powermanager unit, are disabled. The <strong>Intel</strong> PXA27x processor'sPWR_EN output pin de-asserts to optionally disable theexternal low-voltage power supplies to the <strong>Intel</strong> PXA27xprocessor’s low-voltage domains. The <strong>Intel</strong> PXA27xprocessor’s SYS_EN output pin de-asserts to optionallydisable the external high-voltage power supplies to the <strong>Intel</strong>PXA27x processor's high-voltage domains. All power domainsare powered directly from the backup battery pin, VCC_BATT.The remaining power domains are placed in a low-powerstate where state is retained but no activity is allowed.Recovery is through external, and selected internal, wake-upevents. Because the program counter is invalid, recoveryrequires a system reboot (the program counter restarts from0x0, so the core begins execution starting at the reset vector).■■Normal mode: all internal power domains and externalpower supplies are fully powered and functional. Theprocessor clocks are running.Idle mode: Clocks to the CPU are disabled; recovery isthrough interrupt assertion.The <strong>Intel</strong> PXA27x processor provides 37 GPIO inputs that canbe configured as Wake-up events to cause exit from the <strong>Intel</strong>PXA27x processor’s low-power modes (all of the above modesexcept Normal are low-power modes). For example, the <strong>Intel</strong>PXA27x processor has several GPIOs that can act as Wake-upevents when a key is depressed on a Keypad. This wake-up7

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