Wireless Intel SpeedStep Power Manager

White PaperWireless Intel SpeedStep ® Power Managerevent can awaken the Intel PXA27x processor from either theStandby or Sleep low-power modes. Wake-up events couldbe caused by:■■■■■■■■■■KeypressIncoming Voice Phone CallIncoming GPRS DataIncoming SMS MessageHeadset InsertionUSB Cable Insertion and RemovalMMC Insertion and RemovalRTC Wake-upTouchscreen activityShell opening of a “Clam-Shell” phone4.4 Programmable Frequency ChangeManagement (Intel DFM) and ProgrammableVoltage Change Management (Intel DVM)4.4.1 DFMThe Intel PXA27x processor’s core and peripheral clocks are derivedfrom PLLs. The Intel PXA27x processor implements Intel DFM byallowing the core clock to be configured dynamically by software.The core clock frequency can be changed in several ways:■■■Selecting the 13-MHz clock sourceChanging the core PLL frequencyEnabling or disabling turbo mode or half turbo modeSoftware programs the Intel PXA27x processor’s Core ClockConfiguration register (CCCR) to select:■Run Mode to Oscillator Ratio, CCCR[L]—The L-bitdetermines the run frequency by multiplying the externalcrystal oscillator input by L.Software then programs Coprocessor 14, register C6(CLKCFG) to select:■■■■CLKCFG[B]—Fast Bus Mode. If the B-bit is set, thesystem-bus frequency is equal to the run-mode frequencyindicated in CCCR. When the B-bit is cleared, the systembusfrequency is equal to half the run-mode frequencyindicated in the CCCR.CLKCFG[F]—Core Frequency Change. If the F-bit is set,the core PLL is stopped, and then restarted with the newCCCR settings.CLKCFG[T]—Turbo Mode. If the T-bit is set, the CPUoperates at the turbo frequency; when the T-bit is cleared,the CPU operates at the run-mode frequency.CLKCFG[HT]—Half-Turbo Mode. If the HT-bit is set,whether the T-bit is set or clear, the CPU operates at theturbo frequency divided by two; when the HT-bit is clear,and the T-bit is clear, the CPU operates at the run-modefrequency; when HT is clear, and T is set, the CPU operatesat the turbo frequency.An automatic frequency change sequence is initiated whensoftware sets CLKCFG[F]. This sequence establishes the valuesin CCCR and the selected modes in CLKCFG.4.4.2 DVMThe Intel PXA27x Processor implements Intel DVM throughits Voltage Manager. The Voltage Manager provides voltagemanagement through use of an I 2 C unit (PWR_I 2 C) that isdedicated to communication with an external PMIC regulator,and through use of a Voltage Change Sequencer.When software initiates a voltage-change mode, the VoltageChange Sequencer can automatically send commands via thePWR_I 2 C unit to an external PMIC regulator. The sequencercan send up to 32 commands, which can be categorized asdynamic commands and static commands:■■Turbo Mode to Run Mode Ratio, CCCR[2N]—The N-bitdetermines the turbo frequency by multiplying the runfrequency by 2N.Alternate Memory Controller Clock Selection,CCCR[A]—If the A-bit is set, the memory controller’s clockfrequency is the same as that of the system bus; if the A-bitis clear, the memory controller’s clock frequency is as shownin Table 1, next page.■■Dynamic commands are executed when the core is running.Static commands are executed after clocks to theprocessor are disabled.The Intel PXA27x processor uses its Power Manager GeneralConfiguration Register (PCFR), Power Manager Voltage changeControl Register (PVCR), and Power Manager I 2 C CommandRegister File (PCMDx) to define and control a voltage changesequence:8