Wireless Intel SpeedStep Power Manager

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White PaperWireless Intel SpeedStep ® Power Managerevent can awaken the Intel PXA27x processor from either theStandby or Sleep low-power modes. Wake-up events couldbe caused by:■■■■■■■■■■KeypressIncoming Voice Phone CallIncoming GPRS DataIncoming SMS MessageHeadset InsertionUSB Cable Insertion and RemovalMMC Insertion and RemovalRTC Wake-upTouchscreen activityShell opening of a “Clam-Shell” phone4.4 Programmable Frequency ChangeManagement (Intel DFM) and ProgrammableVoltage Change Management (Intel DVM)4.4.1 DFMThe Intel PXA27x processor’s core and peripheral clocks are derivedfrom PLLs. The Intel PXA27x processor implements Intel DFM byallowing the core clock to be configured dynamically by software.The core clock frequency can be changed in several ways:■■■Selecting the 13-MHz clock sourceChanging the core PLL frequencyEnabling or disabling turbo mode or half turbo modeSoftware programs the Intel PXA27x processor’s Core ClockConfiguration register (CCCR) to select:■Run Mode to Oscillator Ratio, CCCR[L]—The L-bitdetermines the run frequency by multiplying the externalcrystal oscillator input by L.Software then programs Coprocessor 14, register C6(CLKCFG) to select:■■■■CLKCFG[B]—Fast Bus Mode. If the B-bit is set, thesystem-bus frequency is equal to the run-mode frequencyindicated in CCCR. When the B-bit is cleared, the systembusfrequency is equal to half the run-mode frequencyindicated in the CCCR.CLKCFG[F]—Core Frequency Change. If the F-bit is set,the core PLL is stopped, and then restarted with the newCCCR settings.CLKCFG[T]—Turbo Mode. If the T-bit is set, the CPUoperates at the turbo frequency; when the T-bit is cleared,the CPU operates at the run-mode frequency.CLKCFG[HT]—Half-Turbo Mode. If the HT-bit is set,whether the T-bit is set or clear, the CPU operates at theturbo frequency divided by two; when the HT-bit is clear,and the T-bit is clear, the CPU operates at the run-modefrequency; when HT is clear, and T is set, the CPU operatesat the turbo frequency.An automatic frequency change sequence is initiated whensoftware sets CLKCFG[F]. This sequence establishes the valuesin CCCR and the selected modes in CLKCFG.4.4.2 DVMThe Intel PXA27x Processor implements Intel DVM throughits Voltage Manager. The Voltage Manager provides voltagemanagement through use of an I 2 C unit (PWR_I 2 C) that isdedicated to communication with an external PMIC regulator,and through use of a Voltage Change Sequencer.When software initiates a voltage-change mode, the VoltageChange Sequencer can automatically send commands via thePWR_I 2 C unit to an external PMIC regulator. The sequencercan send up to 32 commands, which can be categorized asdynamic commands and static commands:■■Turbo Mode to Run Mode Ratio, CCCR[2N]—The N-bitdetermines the turbo frequency by multiplying the runfrequency by 2N.Alternate Memory Controller Clock Selection,CCCR[A]—If the A-bit is set, the memory controller’s clockfrequency is the same as that of the system bus; if the A-bitis clear, the memory controller’s clock frequency is as shownin Table 1, next page.■■Dynamic commands are executed when the core is running.Static commands are executed after clocks to theprocessor are disabled.The Intel PXA27x processor uses its Power Manager GeneralConfiguration Register (PCFR), Power Manager Voltage changeControl Register (PVCR), and Power Manager I 2 C CommandRegister File (PCMDx) to define and control a voltage changesequence:8
Wireless Intel SpeedStep ® Power ManagerWhite Paper■■■■Frequency/Voltage Change, PCFR[FVC]—If the FVC bitis set, a frequency change sequence (DFM) also triggers avoltage change sequence (DVM).Read Pointer, PVCR[RP]—The read pointer field in thePVCR points to the PCMD register location that contains acommand or the first command of multiple commands thatare to be sent to the external regulator via the PWR_I 2 C. Thecommand sequence can start from any one of 32 PCMDregisters. After a command is sent out, the Read Pointerincrements to point to the next PCMD register location. Theread pointer is not incremented if the current command is thelast command, as indicated by PCMD[LC] set.Delay Command Execution, PCMD[DCE]—If the DCE bitis set in the current PCMD, a counter (set by the commanddelay bits in PVCR) waits for a programmable number of13-MHz processor-oscillator cycles before continuingexecution of the command. This is useful if a longer periodbetween commands is required.Multi-Byte Command, PCMD[MBC]—If the MBC bit isset, the voltage change sequencer continues sending byteswith no delay or handshaking with the power manager unituntil a command with the MBC bit clear is executed.■Last Command, PCMD[LC]—If the LC bit is clear, thevoltage-change sequencer expects the PCMD register at thenext higher address to contain an additional command. If theLC bit is clear in PCMD31, the PVCR Read Pointer rolls overto PCMD0 after executing the command in PCMD31. Whenthe LC bit is set, the Voltage Change Sequencer considersthe current command to be the last one and finishes afterexecution completes. Each voltage change commandsequence must be terminated by setting the LC bit of thelast command in the sequence. The PVCR Read Pointer isnot incremented if the LC bit is set.4.4.3 COUPLING VOLTAGE CHANGEWITH FREQUENCY CHANGEA frequency change (clock source change or core PLLfrequency change) may be used to change the frequencyof the core, system bus, memory controller, and LCD controllerto a value not available with turbo or fast-bus modes. Thisfrequency change can be coupled with a voltage change bysetting PCFR[FVC]. Similarly, a voltage change can be coupledwith a change to or from fast-bus mode.4.5 Programmable Operating FrequenciesThe Intel PXA27x processor’s programmable operatingfrequencies are shown in Table 1.Core RunFrequencyCLKCFG[T]Core TurboFrequencyCLKCFG[T]CLKCFG[HT]CCCR[L]CCCR[2N]System BusCLKCFG[B]CLK_MEM(Memory Controller)CCCR[A]SDCLKSDRAM ClocksMDREFR[KxDB2] ††Synchronous FlashMDREFR[K0DB4]MDREFR[K0DB2]LCD91.0 † 0 — — 0 7 2 45.0 0 91.0 0 45.0 1 22.5 1104.0 0 104.0 1 0 8 2 104.0 1 104.0 1 104.0 0 52.0 0156.0 0 156.0 1 1 8 6 104.0 1 104.0 1 104.0 0 52.0 0104.0 0 312.0 1 0 8 6 104.0 1 104.0 1 104.0 0 52.0 0208.0 0 208.0 1 0 16 2 208.0 1 208.0 1 104.0 1 52.0 1208.0 0 312.0 1 0 16 3 208.0 1 208.0 1 104.0 1 52.0 1208.0 0 416.0 1 0 16 4 208.0 1 208.0 1 104.0 1 52.0 1208.0 0 520.0 1 0 16 5 208.0 1 208.0 1 104.0 1 52.0 1208.0 0 624.0 1 0 16 6 208.0 1 208.0 1 104.0 1 52.0 11 91.01 52.01 52.01 52.0X 104.0X 104.0X 104.0X 104.0X 104.0† L=7 (Core = 91.0 MHz) must be strictly used as the bootup frequency and immediately reconfigured to one of the other frequency points.†† KxDB2 represents K1DB2 and K2DB2Table 1. Clock Frequencies9
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Wireless Intel SpeedStep Power Manager

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