Wireless Intel SpeedStep Power Manager

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White PaperWireless Intel SpeedStep ® Power ManagerApplicationsOS ServicesRadioKernel OS PM PMCommUSBPowerMgmtProtocol Stack L2/L3AudioProtocol Stack L1HALPMICAudioUSBDriverMSLDriverMSLAT/APEX InterfaceComm FWPM Component PM Enhanced PM Optional OS ComponentFigure 4. Communications Subsystemdevice drivers can be as simple as: enable the clock to Device #1and then enable Device #1, and/or disable Device #2 and thendisable the clock to Device #2. The device drivers must transitionthe devices into the specified power state and prepare thedevices for the next event.The Policy Manager also uses the DPI to communicate a newfrequency and a new voltage (that meets system performancerequirements with minimum power consumption) to the IntelPXA27x processor’s Power I 2 C (PWR_I 2 C) device driver. ThePWR_I 2 C unit within the Intel PXA27x processor uses Intel DVMto control the physical change to the specified voltage.Frequency can be controlled via Intel DFM in conjunction withIntel DVM. Each device driver has the flexibility to request thatthe Policy Manager change the power state, e.g., the batterydriver can monitor battery thresholds and then use its DPI tonotify the Policy Manager of a needed power state change.Each device driver must be designed to be compatible with thePower Manager software.3.2 Applications Programming Interface (API)Applications that have a dependency on performance can usethe APIs to request the Policy Manager to quickly determinea frequency and a voltage that meets immediate performanceneeds with minimum power consumption. The Policy Manageruses the DPI to communicate a needed frequency and voltageto the Power I 2 C (PWR_I 2 C) device driver. The PWR_I 2 C Unitwithin the Intel PXA27x processor uses Intel DVM to controlthe physical change to the needed voltage. Frequency can becontrolled via Intel DFM in conjunction with Intel DVM. Thepower savings that are realized by applications that are optionallyenhanced to use the Power Manager software supplement thepower savings that are realized with the help of the Idle Profiler,Performance Profiler, and DPIs.3.3 Cellular Processor InterfaceCommunications software, shown on the right side of Figure 4,runs on an Intel Cellular Processor. The power managementcomponent of the communications software manages powerfor the communications subsystem and it maintains its ownstate machine. This power management component interfacesto the L1/L2/L3 layers of the communications protocol stackand it has specific run/low-power mode duty cycles associatedwith each of its states for both GSM and GPRS.A physical link connects the application subsystem with thecommunications subsystem. An Intel ® Mobile Scalable Link (Intel ® MSL) can connect the Intel PXA27x processor in theapplications subsystem with an Intel CommunicationsProcessor in the communications subsystem. Alternatephysical links could use a UART or a Synchronous Serial Port.Communications device drivers that run on the applicationssubsystem are clients of the Power Manager software and theoperating system’s native power management component.These communications device drivers receive notifications fromthe Power Manager software and operating system’s powermanagement component on needed power state transitions.For example, when the OS goes into the Standby power state,these steps are performed:6
Wireless Intel SpeedStep ® Power ManagerWhite Paper1. The Power Manager software notifies the communicationsdriver of the need to transition the communicationssubsystem into the Standby power state.2. The communications driver sends a “change to Standby powerstate” message over the Intel MSL to the communications powermanagement component of the communications subsystem.3. The communications subsystem enters the Standby powerstate and prepares itself to wake-up the applications subsystemif the communications subsystem transitions into a newstate that requires processing in the applications subsystem.Similarly, for dynamic performance and power scaling, thecommunications device driver is notified about a frequencyand voltage change, and in turn notifies the communicationssoftware of such via the Intel MSL.4.0 Intel ® PXA27x—Low PowerEnhancementsThe Intel PXA27x processor implements Wireless IntelSpeedStep ® Technology in hardware by providing the following:4.1 Reset Sources■■■■■■Power-on ResetHardware ResetWatchdog Timer ResetGPIO ResetReset on exit from Sleep modeReset on exit from Deep-Sleep mode4.2 Clock Gating for PeripheralsThe Intel PXA27x processor not only allows each of itsperipherals to be independently enabled or disabled, it alsoallows the clock to each peripheral to be independently gatedon or off.4.3 Power Modes■■■■Deep Idle mode: This mode can be entered only after thecore frequency has been changed to 13 MHz. Clocks to theCPU are disabled; recovery is through interrupt assertion.Standby mode: All internal power domains except VCC_RTCand VCC_OSC are placed in a low-power mode where stateis retained but no activity is allowed. The clock sources maybe disabled. Some of the internal power domains can bepowered off, and both PLLs are disabled. Recovery is throughexternal and selected internal wake-up events.Sleep mode: All internal power domains except VCC_RTCand VCC_OSC (both are internal supplies) can be poweredoff. All clock sources, except those used by the real-timeclock (RTC) and the power manager unit, are disabled. TheIntel PXA27x processor’s PWR_EN output pin de-asserts tooptionally disable the external low-voltage power supplies tothe Intel PXA27x processor's low-voltage domains. Theremaining power domains are placed in a low-power statewhere state is retained but no activity is allowed. Recoveryis through external and selected internal wake-up events.Because the program counter is invalid, recovery requires asystem reboot (the program counter restarts from 0x0, sothe core begins execution starting at the reset vector).Deep Sleep mode: All internal power domains exceptVCC_RTC and VCC_OSC can be powered off. All clocksources, except those used by the RTC and the powermanager unit, are disabled. The Intel PXA27x processor'sPWR_EN output pin de-asserts to optionally disable theexternal low-voltage power supplies to the Intel PXA27xprocessor’s low-voltage domains. The Intel PXA27xprocessor’s SYS_EN output pin de-asserts to optionallydisable the external high-voltage power supplies to the IntelPXA27x processor's high-voltage domains. All power domainsare powered directly from the backup battery pin, VCC_BATT.The remaining power domains are placed in a low-powerstate where state is retained but no activity is allowed.Recovery is through external, and selected internal, wake-upevents. Because the program counter is invalid, recoveryrequires a system reboot (the program counter restarts from0x0, so the core begins execution starting at the reset vector).■■Normal mode: all internal power domains and externalpower supplies are fully powered and functional. Theprocessor clocks are running.Idle mode: Clocks to the CPU are disabled; recovery isthrough interrupt assertion.The Intel PXA27x processor provides 37 GPIO inputs that canbe configured as Wake-up events to cause exit from the IntelPXA27x processor’s low-power modes (all of the above modesexcept Normal are low-power modes). For example, the IntelPXA27x processor has several GPIOs that can act as Wake-upevents when a key is depressed on a Keypad. This wake-up7
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Wireless Intel SpeedStep Power Manager

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