Integrated Transceivers for Optical Wireless Communications

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178 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 11, NO. 1, JANUARY/FEBRUARY 2005Fig. 9.Transimpedance amplifier circuit diagram.B. Receivers1) Transimpedance Amplifier: A major effort has been thedesign of the receiver preamplifier circuit, shown in Fig. 9. Thedetails of its design are outlined in [18]. A transimpedance amplifierstructure is used and consists of a three-stage voltage amplifierwith shunt resistive feedback. This approach provides thebest compromise in terms of noise, gain, and bandwidth, all ofwhich are influenced by the capacitance of the detector. Eachstage of the amplifier is identical and consists of an inverter stagewith diode-connected load. This topology has several design advantages.The inverter, compared to a single device, produces ahigher transconductance for a given bias current. Furthermore,the diode-connected load is used to trade off the gain of the unloadedinverter for increased small-signal bandwidth. The transimpedancebandwidth is governed by the input capacitance,open loop gain of the amplifier, and the feedback resistance. Inorder to account for variances in the detector capacitance andparasitics, a variable feedback resistor is implemented using apositive channel MOS (PMOS) transistor biased in the linear region.The resistance can be varied by applying a voltage biasto the gate of the transistor in order to achieve the required bandwidthand maintain stability over a range of 2–10 pF of capacitanceat the input.The preamplifier circuit was fabricated using a 0.7- mCMOS process technology, offered through the Europracticeinitiative. With a total input capacitance (including detectorand parasitics) of 10 pF, the transimpedance amplifier achievesa measured bandwidth of 217 MHz and transimpedance gainof 4.2 k . This compares extremely favorably with [19] whichreports a 156-Mb/s receiver with a 2.5-pF input capacitance.Noise performance of the circuit was measured by comparingthe output noise spectra with and without input signal in orderto remove the effect of measurement noise, as proposed byCarruthers [20]. The measured input-referred noise currentdensity is 5.92 pA Hz. At a bandwidth of 217 MHz, usingthe measured detector responsivity of 0.39 A/W, this impliesa sensitivity of approximately 29 dBm at 980 nm. Fig. 10(a)shows a 310-Mb/s eye diagram receiver output, showing goodperformance at this data rate. Calculations indicate that avariation in optical power of approximately 22 dB can be accommodatedby the preamplifier, but due to the limited sourcepower available, this was only verified by measurement over a7.5-dB range.Fig. 10. Eye diagrams for transimpedance amplifier operating at 310 Mb/s andlater design operating at 1 Gb/s.2) Gigabit Receiver: In order to investigate extending theproposed receiver architecture to Gb/s data rates, a receiver ICoperating at 1 Gb/s was developed and realized in a 0.35- mCMOS process. The chip includes two transimpedance amplifierstages; one is a common-source input stage, and the othera current-mode common-gate input stage. The low input resistanceof the common-gate stage has many potential advantages,as the large detector capacitance can be decoupled fromthe bandwidth and gain of the preamplifier, ultimately leadingto lower noise. Theoretical analysis presented in [21] showsthat the performance improvement offered by the common-gatestage is limited when implementing the receiver in a standardCMOS technology operating at a single, low supply voltage.Furthermore, isolating the large photodiode capacitances expectedin optical wireless receivers can lead to large junctioncapacitances that further degrade performance and hinder designoptimization. Electrical measurements were carried out onboth preamplifier topologies using a detector emulation circuitat the input of each channel with an associated capacitance of 6pF. Best results were achieved on the common-source channel.The common-source preamplifier achieves a gain of 44.6 dB,3-dB bandwidth of 500 MHz, and an input-referred currentnoise power spectral density (PSD) of 14.8 pA Hz; good eyeopenings have been demonstrated at bit rates up to 1 Gb/s asshown in Fig. 10(b).
O’BRIEN et al.: INTEGRATED TRANSCEIVERS FOR OPTICAL WIRELESS COMMUNICATIONS 179Fig. 11. (a) Diversity receiver block diagram. (b) Transconductance amplifierschematic.3) Diversity Receiver: In order to recover data from the incomingoptical power, the signal from the desired detector orgroup of detectors must be routed to the data recovery circuit.A combiner circuit that allows arbitrary combination of signalsfrom three preamplifiers has been designed, fabricated, andtested. Fig. 11(a) shows a block diagram of the selector combinercircuit. Each detector drives a dedicated preamplifier circuit.Channel selection and combination is performed using acurrent bus-bar approach. The preamplifier circuit, with outputvoltage Vpre, drives a transconductance stage (Gm) producingan output current Iout.The transconductance stage is shown in Fig. 11(b) and is implementedusing an n-type differential pair with an active currentmirror load. The preamplifier output signal Vpre is applieddirectly to the noninverting input terminal and passed throughan RC low-pass filter to supply the preamplifier dc output signalto the inverting input terminal. This low-pass filter and differentialpair combination has a bandpass filtering characteristic withthe lower cutoff frequency set by the low-pass filter cutoff. Interms of noise performance, this transconductance approach canconsiderably reduce low-frequency 1 receiver noise and enhancesensitivity. To avoid signal distortion, the low-pass filtercutoff frequency is set well below frequencies expected at thereceiver input.The output current signals are steered by switches to a currentbus-bar, which serves as a current summing junction. Theseswitches are controlled by the SEL signals derived from the externalcontrol circuit. The SEL signal is assigned based on thesignal level Vpre at the output of the preamplifier circuit. Theselector–combiner circuit can select the channel with the bestsignal-to-noise ratio (so-called select best combining) or allchannels having appreciable signal levels and combine themwith equal gain. Details of this architecture can be found in [21].Fig. 12. Received electrical signals for three-channel combiner operating at200 Mb/s, showing two individual channel signals and the resulting combinedsignal.This was fabricated using a 0.7- m CMOS process technology.Fig. 12 illustrates equal gain combining of two input signals.4) Seven-Channel Receiver: Flip-chip packaging allowsintegration of optoelectronic ICs directly to the supportingCMOS electronics with low parasitics, enabling significantimprovements to the design and implementation of scalableoptical receiver arrays. The flip-chip compatible receiver ICwas realized using a 0.7- m CMOS process. The chip is arrangedinto three separate receiving segments to give greaterflexibility in performing optical measurements. There are twothree-channel combiner circuits consisting of the preamplifierand selector–combiner circuits presented above; a single channelwith preamplifier and buffer circuit is also included. Integrationof this chip with the detector array is detailed in Section VII.VI. OPTICAL SYSTEM DESIGNA. Design ConsiderationsThe optical system can be thought of as performing a spaceanglemappingatthetransmitterandtheinversemappingatthereceiver.Transmitteropticalelementsarerelativelystraightforwardto design, and the system is largely constrained by the receiver.
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Integrated Transceivers for Optical Wireless Communications

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