VS1063 Hardware Guide - VLSI Solution

More documents

Recommendations

Info

VS1063a HW Guide6.2 VS1063a Hardware ADC Audio PathsMICNMICPLINE1LINE2MicrophoneamplifierMultiplexerADC6 VS1063A HARDWARE AUDIO PATHSADCdecimatorFigure 2: VS1063a ADC and DAC data paths with some data registersFigure 1 presents the VS1063a Hardware ADC audio paths.RegistersADC_DATA_LEFTADC_DATA_RIGHTAnalog audio may be fed upto two channels: one as a differential signal to MICN/MICP or as aone-sided signal to Line1, and the other as a one-sided signal to Line2.If microphone input for the left channel has been selected, audio is fed through a microphoneamplifier and that signal is selected by a multiplexer.Audio is then downsampled to one of four allowed samplerates: XTALI/64, XTALI/128, XTALI/256or XTALI/512. With the nominal 12.288 MHz crystal, these correspond to 192, 96, 48 or 24 kHzsamplerates, respectively (Chapter 7.12).If the “3 MHz” option bit SS_AD_CLOCK in register SCI_STATUS has been set to 1, thensamplerates are divided by two, so the nominal samplerates become 96, 48, 24 and 12 kHz.PRELIMINARYVersion: 0.40, 2011-09-02 10
7 Hardware RegistersVS1063a HW Guide7 HARDWARE REGISTERSVS1063a registers are memory mapped to X data memory, starting from address 0xC000.7.1 Serial Control Interface (SCI)SCI registers are mapped to X memory addresses between 0xC000..0xC00F. In addition tothese registers, there is one in address 0xC010, called SCI_CHANGE.Only 3 of these 17 registers contain direct hardware control. Those registers and their hardwareregisters bits are described in this section. For documentation of the software register bits, seethe VS1063a Datasheet.7.1.1 SCI RegistersSCI registers, prefix SCI_Reg Type Reset Abbrev[bits] Description0xC000 rw 0x4000 2 MODE Mode control0xC001 rw 0x000C 2 STATUS Status of VS1063a0xC010 r xxxx CHANGE[5:0] Last SCI access address1 Firmware changes the value of this register immediately to 0x4800.2 Firmware changes the value of this register immediately to 0x48 (analog enabled), and aftera short while to 0x40 (analog drivers enabled).7.1.2 Mode SCI_MODE (RW)Name Bit Function Value DescriptionSM_DACT 8 DCLK active edge 0 rising1 fallingSM_SDIORD 9 SDI bit order 0 MSb first1 MSb lastSM_SDISHARE 10 Share SPI chip select 0 no1 yesSM_SDINEW 11 VS1002 native SPI modes 0 no1 yesSM_LINE1 14 MIC / LINE1 selector 0 MICP1 LINE1SM_CLK_RANGE 15 Input clock range 0 12..13 MHz1 24..26 MHzPRELIMINARYVersion: 0.40, 2011-09-02 11
Page 1 and 2: VS1063a HW GuideVS1063a HARDWARE GU
Page 3 and 4: ContentsVS1063a HW GuideCONTENTSVS1
Page 5 and 6: List of FiguresVS1063a HW GuideLIST
Page 7 and 8: VS1063a HW Guide4 The VSDSP Process
Page 9: VS1063a HW Guide6 VS1063a Hardware
Page 13 and 14: VS1063a HW Guide7 HARDWARE REGISTER
Page 15 and 16: 7.4 PLL ControllerVS1063a HW Guide7
Page 17 and 18: VS1063a HW Guide7.5 General-Purpose
Page 19 and 20: VS1063a HW Guide7.7 Universal Async
Page 21 and 22: VS1063a HW Guide7 HARDWARE REGISTER
Page 23 and 24: 7.8.3 Configuration TIMER_ENABLEVS1
Page 25 and 26: VS1063a HW Guide7.10 Analog-to-Digi
Page 27 and 28: VS1063a HW Guide7.12 Sidestream Sig
Page 29: VS1063a HW Guide9 Contact Informati

VS1063 Hardware Guide - VLSI Solution

Create successful ePaper yourself

Delete template?

Save as template?