2 The scaling of MOSFETs, Moore's law, and ITRS

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2continued to be defined as 70% dimension reduction per node or approximately 50%reduction per two nodes. The “technology-node-cycle” is the period of time in which anew technology node is introduced.In addition to the scaling of the gate length, the oxide thickness is anothercritical parameter, which has been aggressively scaled down in order to achieve asufficient drive current and to control short channel effect. The later can be achieved bymaintaining the electrostatic control of the channel potential by the gate.Figure 2:4 shows the technology half pitch (hp) and gate length trends adoptedin the ITRS’03 edition. Beyond year 2007 the two year cycle delays by another year andis expected to be three years until the end the present roadmap projection time-line andprobably beyond. The physical gate length is conventionally adapted as minimumfeature size regarding the individual devices.1000DRAM ½ PitchMPU Physical L gMPU/ASIC ½ PitchMPU Printed L gDimension [nm]100102 year cycle 3 year cycle1199219962000200420082012Year of production20162020Figure 2:4 Technology half-pitch and gate length trends.16
The scaling of MOSFETs, Moore’s law, and ITRS Chapter 22.2 The scaling rules for conventional MOSFETsIn the preceding sections the technology roadmap and the Moore’s law havebeen discussed in order to examine their role in pursuing transistor scaling, and aboveall in highlighting scaling’s unprecedented contributions to the enormous advance ofsemiconductor technology. Without the extraordinary miniaturization of transistors, itwould be impossible to produce higher volumes of faster devices operating at lowerpower. Nobody in the semiconductor industry disputes this state of affairs. This sectionfurther introduces the theory and practice of the scaling process. It begins by reviewingsome of the classic papers on the constant field and generalised device scaling rules,followed by detailed analysis of advantages and shortcomings of both rules.2.2.1 Constant field scalingDennard at al. presented their pioneering research work on the scaling ofMOSFET devices at the International Electron Device Meeting (IEDM) 1972 [2.14] andpublished a comprehensive paper on the scaling of MOS transistors in 1974 [2.15], fromwhich the “constant field scaling” theory has emerged. The basic principle which theyemploy is that in order to increase the performance of a MOSFET we must reducelinearly the size of the transistor, together with the supply voltage, and increase thedoping concentration in a way which keeps the electric field in the device constant -hence the name “constant field scaling” (figure 2.5).LgVddt OXκLGκVddκt OXLchκNaL chκNaFigure 2: 5 Illustration of MOSFET miniaturisation. The sketch on the right hand is the scaled deviceaccording to the constant field rule. (Reference [2.15])17
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2 The scaling of MOSFETs, Moore's law, and ITRS

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