2 The scaling of MOSFETs, Moore's law, and ITRS

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2However, not all of these categories and data are relevant to this research.Therefore, in this sub-section we only concentrate on the high performance devices,which are in the heart of this work. The summarised data of device dimensions andelectrical parameters for high performance devices depicted in tables 2:1 (near-termyears) and 2:2 (long-term years) have been adopted as a guide for the scaling of the 35nm MOSFET described in chapter 4.The carefully calibrated 35 nm gate length MOSFETs manufactured by Toshiba[2.12]) were used as a basis for further scaling to gate lengths of 25, 18, 13, and 9 nmtransistors. The overall calibration and scaling methodology and results are presented inchapter 3 and 4 respectively. The dimensions of the 35 nm MOSFET physical gatelength used for this work are not characteristics of particular node on the ITRSroadmap. It’s performance, I on = 676µA/µm, I off = 100nA at V dd = 850mV and designparameters, t ox = 1.2 nm x j = 20 nm are close to the 37 nm high performance devicerequired for the 90 nm node and 80 nm technology generations.Year of Production 2010 2012 2013 2015 2016 2018Technology Node hp45 hp32 hp22DRAM ½ Pitch (nm) 45 35 32 25 22 18MPU/ASIC M1 ½ Pitch (nm) 54 42 38 30 27 21MPU/ASIC Poli Si ½ Pitch (nm) 45 35 32 25 22 18MPU Printed L g (nm) 25 20 18 14 13 10MPU Physical L g (nm) 18 14 13 10 9 7Equivalent t ox (nm) 0.7 0.7 0.6 0.6 0.5 0.5V dd (HP) (V) 1 0.9 0.9 0.8 0.8 0.5Off current , I off [µA/µm] 0.1 0.1 0.3 0.3 0.5 0.5Drive Current, I on [µA/µm] 1900 1790 2050 2110 2400 2190HP NMOS intrinsic delay τ [ps] 0.39 0.3 0.26 0.18 0.15 0.11Relative intrinsic speed, 1/τ 3.06 4.05 4.64 6.8 8.08 10.77Logic gate delay [ps] 9.88 7.47 6.55 4.45 3.74 2.81DRAM cell size [µm 2 ] 0.1222 0.0077 0.0061 0.0038 0.0025 0.0016S/D extension depth x j [nm] ‡ 7.2 11.2 10.4 8.0 7.2 5.1Table 2:2 The long - term years (2010-2018)‡ The extension depth (x j ) is calculated with the assumption of introducing new device structures beyondyear 2007, like fully depleted SOI and multi gate device structures. (ITRS 2003 edition)14
The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2Although the electronics industry prefers to continue as long as possible with thescaling of conventional MOSFETs, there is “Red Brick Wall” to this process unlessthere is a major technological breakthrough. High channel doping, which degrades thedevice performance, and ultra thin gate oxides, which introduce unacceptable gateleakage, are likely to prompt a replacement to conventional MOSFETs somewherebeyond the 65nm technology node. Among the replacement candidates are, for example,ultra-thin body SOI and multiple gate devices complimented by the introduction ofstrained silicon in the channel region to enhance the carrier mobility, and highpermittivity materials in the gate stack in order to suppress gate leakage. Some of thecritical scaling limitation factors will be examined more closely in the next sections ofthis chapter.2.1.4 The scaling factors and technology trendsThe scaling factor of κ ≈ 2, related to a 70% size reduction of the majortechnology nodes every two years, has been adapted for the linear scaling of devicedimensions in this work. The other scaling constant, αfor the electric field andpotential used in the generalised scaling scenario [2:10] is not specified on the roadmap. However, it can be calculated from the supply voltages (V dd ), which are specifiedin the roadmap for corresponding feature sizes and the linear scaling factor κ as:α V 'V ' = V ⇒ α = κ(2.3)κ V'V is the new supply voltage given in the technology roadmap and V is the supplyvoltage of the previous generation. It should be noted that in some papers [2.13], thelinear scaling factor has been decomposed to separate dimensional scaling parameters inthe so called “selective scaling case”, which introduces different values for vertical,horizontal, and lateral dimensions multipliers. However, in this work, the generalizedscaling rule has been adopted as a principal guiding rule for device scaling. A review ofthe different scaling approaches is presented in the next section.Unlike the previous editions of ITRS, no prediction of the technologyacceleration has been made in its latest edition (ITRS’03). Also, as illustrated in figure2.4, in the last ITRS edition, the technology generations are predicted to shift from thepresent two-year cycle to a three-year cycle trend around 2007. The technology node15
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2 The scaling of MOSFETs, Moore's law, and ITRS

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