2 The scaling of MOSFETs, Moore's law, and ITRS

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The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2GateFigure 2:11 The overall gate tunnelling current is the sum all the components tunnelling current namelythe source-to-gate, drain-to-gate and channel to gate currents (reference [2.46])In the previous generations of MOSFET devices, the contribution of gate oxideleakage current to the overall leakage current has not been substantial. However, this isnot the case for the present and the next generation of devices. As shown in figure 2.11,in addition to the tunnelling current from the channel I gc , the fringing currents from thegate overlap with the source extension-I gs and drain extension-I gd also contribute to thetotal gate leakage current [2.46]. Bearing in mind that the main source of standby powerdrawn in CMOS circuits originates from the off-state current, substantial increase in offcurrent due to direct tunnelling through the gate dielectric should be consideredseriously during the design of devices or power optimization in circuits [2.47]. Theapplication dependant power constraint as one of the main limitations of MOSFETscaling will be discussed in section 2.3.3The cumulative gate tunnelling current density can be approximated by equation(2.4) [2.45]:[ EFn1EC1E kT ][ ]E4πqm exp( ) / 11kTb⎡ − − + ⎤JDT= ( )ln3CE dEh ∫ τ ⎢ ⎥exp( E0 ⎣Fn2 − E2− E) / kT + 1(2.11)⎦30
The scaling of MOSFETs, Moore’s law, and ITRS Chapter 2where m 1 , and is the electron effective tunnelling mass E Fn1 the electron Fermi level, andE c1 is the bottom of conduction band in Si, and E Fn2 , and E c2 in the polysilicon region.I g0.0 0.5 1.0 1.5 2.0 2.5 3.0t ox1.69x10 3 0.4I g[nA/um]6x10 33x10 30J g[A/cm 2 ]10 6 Model t ox=1nm10 4 Data1.5 nm10 210 02 nm2.2 nm10 -22.6 nm10 -42.9 nm3.3 nm3.5 nm10 -610 -8Gate Voltage [V]3.6 nm10 20 30 40 50L g[nm]1.20.8t ox[nm]Figure 2:12 The relationship between the gate leakage current and the physical gate length. Inset: thegate current density for various oxide thicknesses as a function of gate voltage. Data from ITRS (2004 update)and the inset graph is adapted from reference. [2.48]Figure 2:12 illustrates the relationship between gate length reduction and thegate oxide thickness which are required for the 90nm technology node and beyond. Thefigure also shows the increase of the gate leakage current density for various oxidethicknesses. The increase in leakage current is exponential [2.49]. For example, for gatelengths below 10 nm, and corresponding oxide thicknesses of 0.4 - 0.5, nm the leakagecurrent reaches about 8-10 µA/µm provided that SiO 2 is used as a gate dielectricmaterial. This amount of leakage current can affect transistor integration in highperformance digital systems where low power dissipation per area is a critical issueduring the stand-by mode of operation.The inset in figure 2:12 compares according to [2:48] the experimental data andthe calculated gate tunnelling current density for a range of oxide thickness as a function31
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2 The scaling of MOSFETs, Moore's law, and ITRS

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