Lead and Lag Compensator Design using Root Locus

EE 3CL4, §6 

1 / 38 

Tim Davidson 

Compensators 

Lead 

compensation 

Design via Root 

Locus 

Lead Compensator 

example 

Cascade 

compensation 

and 

steady-state 

errors 

Lag 

Compensation 



Lag compensator 

example 

Insights 

EE3CL4: 

Introduction to Linear Control Systems 

Section 6: Design of Lead and Lag Controllers using 

Root Locus 

Tim Davidson 

McMaster University 

Winter 2012

EE 3CL4, §6 

2 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

1 Compensators 

2 Lead compensation 

Design via Root Locus 

Lead Compensator example 

Outline 

3 Cascade compensation and steady-state errors 

4 Lag Compensation 

Design via Root Locus 

Lag compensator example 

5 Insights

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 


• Early in the course we provided some useful guidelines 

regarding the relationships between the pole positions 

of a system and certain aspects of its performance 

• Using root locus techniques, we have seen how the 

pole positions of a closed loop can be adjusted by 

varying a parameter 

• What happens if we are unable to obtain that 

performance that we want by doing this? 

• Ask ourselves whether this is really the performance 

that we want 

• Ask whether we can change the system, 

say by buying different components 

• seek to compensate for the undesirable aspects of the 

process

EE 3CL4, §6 

5 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Cascade compensation 

• Usually, the plant is a physical process 

• If commands and measurements are made electrically, 

compensator is often an electric circuit 

• General form of the compensator is 

Gc(s) = Kc 

�M i=1 (s + zi) 

�n j=1 (s + pj) 

• Therefore, the cascade compensator adds open loop 

poles and open loop zeros 

• These will change the shape of the root locus

EE 3CL4, §6 

6 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Compensator design 

• Where should we put new poles and zeros to achieve 

desired performance? 

• That is the art of compensator design 

• We will consider first order compensators of the form 

Gc(s) = Kc(s + z) 

(s + p) = ˜ Kc(1 + s/z) 

(1 + s/p) , where ˜ Kc = Kcz/p 

• with the pole −p in the left half plane 

• and the zero, −z in the left half plane, too 

• For reasons that will soon become clear 

• when |z| < |p|: phase lead network 

• when |z| > |p|: phase lag network

EE 3CL4, §6 

8 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lead compensation 

Gc(s) = Kc(s + z) 

(s + p) 

with |z| < |p|. That is, zero closer to origin than pole 

Let p = 1/τ and z = 1/(αleadτ). Since z < p, αlead > 1. 

Define ˜ Kc = Kcz/p = Kc/αlead. Then 

Gc(s) = Kc(s + z) 

(s + p) = ˜ Kc(1 + αleadτs) 

(1 + τs)

EE 3CL4, §6 

9 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lead compensation 

With |z| < |p|, αlead > 1, Gc(s) = Kc(s+z) 

(s+p) = ˜ Kc(1+αleadτs) (1+τs) 

• Frequency response: 

• Bode diagram 

Gc(jω) = ˜ Kc(1 + jωαleadτ) 

(1 + jωτ) 

• Between ω = z and ω = p, |Gc(jω)| ≈ ˜ Kcωαleadτ 

• What kind of operator has a frequency response with 

magnitude proportional to ω? Differentiator 

• Note that the phase is positive. Hence “phase lead”

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

A passive phase lead network 

Homework: Show that V 2(s) 

V 1(s) has the phase lead 

characteristic

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Active lead and lag networks 

Here’s an example of an active network architecture.

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Principles of Lead design via 

Root Locus 

• The compensator adds poles and zeros to the P(s) in 

the root locus procedure. 

• Hence we can change the shape of the root locus. 

• If we can capture desirable performance in terms of 

positions of closed loop poles 

• then compensator design problem reduces to: 

• changing the shape of the root locus so that these 

desired closed-loop pole positions appear on the root 

locus 

• finding the gain that places the closed-loop pole 

positions at their desired positions 

• What tools do we have to do this? 

• Phase criterion and magnitude criterion, respectively

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Root Locus Principles 

• The point s0 is on the root locus of P(s) if 1 + KP(s0) = 0. 

• In first order compensator design with G(s) = K G 

and Gc = Kc(s+z) 

(s+z) 

(s+p) , we have P(s) = (s+p) 

QM i=1 (s+zi ) 

Qn j=1 (s+pj ) 

Q M 

i=1 (s+zi ) 

Q n 

j=1 (s+pj ) and 

K = KcKG. We will restrict attention to the case of K > 0 

• Phase cond. s0 is on root locus if ∠P(s0) = 180 ◦ + k360 ◦ : 

M� 

(angle from −zi to s0) − 

i=1 

n� 

(angle from −pj to s0) 

j=1 

+ (angle from −z to s0) − (angle from −p to s0) 

= 180 ◦ + k 360 ◦ 

• Mag. cond. If s0 satisfies phase condition, the gain that puts 

a closed-loop pole at s0 is K = 1/|P(s0)|: 

�n j=1 

K = 

(dist from −pj to s0) 

�M i=1 (dist from −zi 

(dist from −p to s0) 

× 

to s0) (dist from −z to s0)

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

RL design: Basic procedure 

1 Translate design specifications into desired positions of 

dominant poles 

2 Sketch root locus of uncompensated system to see if desired 

positions can be achieved 

3 If not, choose the positions of the pole and zero of the 

compensator so that the desired positions lie on the root 

locus (phase criterion), if that is possible 

4 Evaluate the gain required to put the poles there 

(magnitude criterion) 

5 Evaluate the total system gain so that the steady-state error 

constants can be determined 

6 If the steady state error constants are not satisfactory, repeat 

This procedure enables relatively straightforward design of 

systems with specifications in terms of rise time, settling time, and 

overshoot; i.e., the transient response. 

For systems with steady-state error specifications, Bode (and 

Nyquist) methods may be more straightforward (later)

EE 3CL4, §6 

15 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lead Comp. example 

Consider a case with G(s) = 1 

s(s+2) and H(s) = 1. 

Design a lead compensator to achieve: 

• damping coefficient ζ = 0.45 and 

• velocity error constant Kv = lims→0 sGc(s)G(s) > 20 

What to do? 

• Let’s draw something. Plot poles of G(s). 

Where should the closed-loop poles be? cos −1 (0.45) ≈ 64 ◦ 

• Note that the settling time is not specified. We are free to 

choose it. However, we need a large Kv which will require 

large gain. Need desired positions far from open loop poles. 

• Let’s start with desired roots ≈ −4 ± j8 

• This pair has Ts = 1 and ωn ≈ 9

EE 3CL4, §6 

16 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lead Comp. example 

• Now where to put the zero and pole? 

• Rule of thumb: put zero under desired root, or just to the left 

• Determine position of the pole using angle criterion 

sum angles from open-loop zeros 

• Hence pole at ≈ −10.6 

• Gain of compensated system: 

− sum angles from open-loop poles = 180 ◦ 

90 − (116 + 104 + θp) = 180 

=⇒ θp = 50 

Prod. dist. from open-loop poles 9(8.25)(10.4) 

≈ = 96.5 

Prod. dist. from open-loop zeros 8 

• Hence compensated open loop: Gc(s)G(s) = 96.5(s+4) 

s(s+2)(s+10.6) 

• Velocity constant: Kv = lims→0 sGc(s)G(s) = 18.2 :(

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Compensated root locus 

Root locus and the step response with the dominant roots at 

their desired locations

EE 3CL4, §6 

18 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

What to do now? 

• We tried hard, but did not achieve the design specs 

• Let’s go back and re-examine our choices 

• Zero position of compensator was chosen via rule of 

thumb 

• Can we do better? 

Yes, but two parameter design becomes trickier. 

• What were other choices that we made? 

• We chose desired poles to be of magnitude ωn ≈ 9 

• We could choose them to be further away 

(faster transient response) 

• By how much? 

• Show that when desired poles have ωn = 10 as well as 

the required ζ = 0.45, then the choice of z = 4.5, 

p = 11.6 and the corresp. Kc results in Kv = 22.7

EE 3CL4, §6 

19 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Outcomes 

• Root locus approach to phase lead design was 

reasonably successful in terms of putting dominant 

poles in desired positions; e.g., in terms of ζ and ωn 

• We did this by positioning the pole and zero of the lead 

compensator so as to change the shape of the root 

locus 

• However, root locus approach does not provide 

independent control over steady-state error constants 

(details upcoming) 

• That said, since lead compensators reduce the DC gain 

(they resemble differentiators), they are not normally 

used to control steady-state error. 

• The goal of our lag compensator design will be to 

increase the steady-state error constants, without 

moving the other poles too far

EE 3CL4, §6 

21 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Cascade compensation 

• Throughout this lecture, and all the discussion on cascade 

compensation, we will consider the case in which H(s) = 1. 

• We will consider first order compensators of the form 

Gc(s) = 

K (s + z) 

(s + p) 

with the pole, −p, and the zero, −z, both in the left half plane 

• when |z| < |p|: phase lead network 

• when |z| > |p|: phase lag network

EE 3CL4, §6 

22 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Steady-state errors 

If closed loop stable, steady state error for input R(s): 

Let G(s) = K G 

R(s) 

ess = lim e(t) = lim s 

t→∞ s→0 1 + GC(s)G(s) 

Q 

i (s+zi ) 

Q 

j (s+pj ) and consider GC(s) = KC(s+z) (s+p) 

• Consider the case in which G(s) is a type-0 system. 

• Steady state error due to a step r(t) = Au(t): 

ess = A 

1+Kposn 

, where 

Kposn = GC(0)G(0) = KCz 

p 

• Note that for a lead compensator, z/p < 1, 

� 

KG i zi 

� 

j pj 

• So lead compensation may degrade steady-state error 

performance

EE 3CL4, §6 

23 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Steady-state error 

• Now, consider the case in which G(s) is a type-1 

system, G(s) = K Q 

G i (s+zi ) 

s Q 

j (s+pj ) 

• Steady-state error due to a ramp r(t) = At: ess = A/Kv, 

where the velocity constant is 

Kv = lim 

s→0 sGc(s)G(s) = K Cz 

p 

� 

KG i zi 

� 

j pj 

• Once again, lead compensation may degrade 

steady-state error performance 

• Is there a way to increase the value of these error 

constants while leaving the closed loop poles in 

essentially the same place as they were in an 

uncompensated system? Perhaps |z| > |p|?

EE 3CL4, §6 

25 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lag compensation 

Gc(s) = Kc(s + z) 

(s + p) 

with |z| > |p|. That is, pole closer to origin than zero 

Let z = 1/τ and p = 1/(αlagτ). Since z > p, αlag > 1. 

Define ˜ Kc = Kcz/p = Kcαlag. Then 

Gc(s) = Kc(s + z) 

(s + p) = ˜ Kc(1 + τs) 

(1 + αlagτs)

EE 3CL4, §6 

26 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Magnitude 

Frequency response 

Gc(jω) = ˜ K C(1 + jωτ) 

(1 + jωαlagτ) 

• Low frequency gain: ˜ K C 

• Corner frequency in denominator at ωp = p = 1/(αlagτ) 

• Corner frequency in numerator at ωz = z = 1/τ 

• ωp < ωz 

• High frequency gain: ˜ K C/αlag = K C 

Phase 

• φ(ω) = atan(ωτ) − atan(αlagωτ) 

• At low frequency: φ(ω) = 0 

• At high frequency: φ(ω) = 0 

• In between: negative, with max. lag at ω = √ zp

EE 3CL4, §6 

27 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Note integrative characteristic 

Bode Diagram

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

A passive phase lag network

EE 3CL4, §6 

29 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Active lead and lag networks 

Here’s an example of an active network architecture.

EE 3CL4, §6 

30 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lag compensator design 

• Lag compensator: Gc(s) = Kc s+z 

s+p . with |z| > |p|. 

• Recall position error constant for compensated type-0 

system and velocity error constant for compensated type-1 

system: 

Kposn = KCz 

p 

� 

KG i zi 

� 

j pj 

, Kv = KCz 

p 

� 

KG i zi 

� 

j pj 

where in the latter case the product in the denominator is 

over the non-zero poles. 

Design Principles 

• We don’t try to reshape the uncompensated root locus. 

• We just try to increase the value of the desired error constant 

by a factor αlag = z/p without moving the poles (well not 

much) 

• Reshaping was the goal of lead compensator design

EE 3CL4, §6 

31 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lag compensator design 

Design principles: 

• Don’t reshape the root locus 

• Adding the open loop pole and zero from the 

compensator should only result in a small change to the 

angle criterion for any point on the uncompensated root 

locus 

• Angles from compensator pole and zero to any point on 

the locus must be similar 

• Pole and zero must be close together 

• Increase value of error constant: 

• Want to have a large value for αlag = z/p. 

• How can that happen if z and p are close together? 

• Only if z and p are both small, i.e., close to the origin

EE 3CL4, §6 

32 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Lag comp. design via Root 


1 Obtain the root locus of uncompensated system 

2 From transient performance specs, locate suitable 

dominant pole positions on that locus 

3 Obtain the loop gain for these points, K = KPK G; 

hence the (closed-loop) steady-state error constant 

4 Calculate the necessary increase. Hence αlag = z/p 

5 Place pole and zero close to the origin (with respect to 

desired pole positions), with z = αlagp. 

Typically, choose z and p so that their angles to desired 

poles differ by less than 1 ◦ . 

6 Set Kc = KP 

What if there is nothing suitable at step 2? 

• Perhaps do lead compensation first, 

• then lag compensation on lead compensated plant. 

i.e., design a lead-lag compensator

EE 3CL4, §6 

33 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Example 

Let’s consider, again, the case with G(s) = 1 

s(s+2) . 

Design a lag compensator to achieve damping coefficient 

ζ = 0.45 and velocity error constant Kv > 20 

Note: we will get a different closed loop from our lead 

design. 

First step, obtain uncompensated root locus, and locate 

desired dominant pole locations

EE 3CL4, §6 

34 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Example 

• Gain required to put closed loop poles in desired position = 

prod. distances from open loop poles 

• That is, K = 2.24 2 = 5. Therefore KP = K /KG = 5 

• Velocity error const: Kv,unc = lims→0 sKPG(s) = K /2 = 2.5 

• The increase required is 20/2.5 = 8 

• That implies must choose p = z/8, where z is chosen to be 

close to the origin with respect to dominant closed-loop poles

EE 3CL4, §6 

35 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Let’s choose z = 0.1. Hence, p = 1/80 

Example

EE 3CL4, §6 

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Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Example 

Compensated open loop transfer function is now 

Gc(s)G(s) = 

5(s + 0.1) 

(s + 1/80) 

1 

s(s + 2) 

Closed-loop poles of compensated system: 

−0.95 ± j1.98, −0.10 

Closed-loop poles of proportionally controlled system: 

−1 ± j2 

What do you expect from the transient response?

EE 3CL4, §6 

38 / 38 

Tim Davidson 



compensation 




example 

Cascade 

compensation 


steady-state 

errors 


Compensation 




example 

Insights 

Insights 

• If we would like to improve the transient performance of 

a closed loop 

• We can try to place the dominant closed-loop poles in 

desired positions 

• One approach to doing that is lead compensator design 

• However, that typically requires the use of an amplifier 

in the compensator, and hence requires a power supply 

• If we would like to improve the steady-state error 

performance of a closed loop 

• We can consider designing a lag compensator to 

provide the required gain 

• However, that typically slows down the transient 

response 

• These insights also have frequency domain 

interpretations, which we will explore later

Lead and Lag Compensator Design using Root Locus

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